;*******************************************************************************
;*
;* Version: 0.00
;* Build: Апрель 11, 2005 19:49:50
;*
;*******************************************************************************

.include "2313def.inc"

;******** Constants ************************************************************

.equ fck = 4000000

;******** Global Register Variables ********************************************

.def sreg = r15
.def a = r16
.def b = r17
.def txcnt = r18
.def txbcnt = r19
.def shift = r20

.def flags = r21
.equ MODE = 0x00
.equ RXD = 0x01

;******** SRAM Variables *******************************************************

.dseg

.org 0x60

.cseg

;******** Reset/Interrupt Vectors **********************************************

.org $000
rjmp reset ; Reset Handler
rjmp irq0 ; IRQ0 Handler
reti ; IRQ1 Handler
reti ; Timer1 Capture Handler
reti ; Timer1 Compare Handler
reti ; Timer1 Overflow Handler
rjmp tim0_ovf ; Timer0 Overflow Handler
reti ; UART RX Complete Handler
reti ; UDR Empty Handler
reti ; UART TX Complete Handler
reti ; Analog Comparator Handler

;******** Setup ****************************************************************

reset:

; Stack Pointer Initialization

ldi a, RAMEND
out SPL, a

; PIO Initialization

ldi a, 0b00000000
out DDRD, a
ldi a, 0b00000000
out PORTD, a
ldi a, 0b11000000
out DDRB, a
ldi a, 0b01000000
out PORTB, a

; Sleep Mode/WatchDog Initialization (PowerDown; WD Disabled)

ldi a, 0b00110010 ; INT0 Falling edge
out MCUCR, a
ldi a, 0b00011000
out WDTCR, a
ldi a, 0b00010000
out WDTCR, a

; Analog Comparator Initialization

ldi a, 0b10000000
out ACSR, a

; Timer0 Initialization

ldi a, 0b00000100 ; CK/256
out TCCR0, a

; Interrupt Initialization

ldi a, (1<<INT0)
out GIMSK, a

cli

;*******************************************************************************
; Main Program
;*******************************************************************************

clr flags
ldi shift, 0x80
sei

main0:
ldi shift, 0x80
andi flags, ~((1<<RXD)+(1<<MODE))
main:
sbrs flags, RXD
rjmp main
cpi shift, 0x33
brne main0
andi flags, ~(1<<RXD)

sbi PORTB, 0x07

ldi ZL, low(code * 0x02)
ldi ZH, high(code * 0x02)
lpm
mov shift, r0
ldi txbcnt, 0x08
ori flags, (1<<MODE)
rjmp main

;*******************************************************************************

irq0:
in sreg, SREG
sbrc flags, MODE
rjmp irq0_1

sbrc flags, RXD ; RX Mode
rjmp irq0_exit
ldi b, 0x14 ; 15us @ 4MHz
irq0_0:
dec b
brne irq0_0
clc
sbic PIND, 0x02
sec
ror shift
brcc irq0_exit
ori flags, (1<<RXD)
rjmp irq0_exit

irq0_1:
lsr shift ; TX Mode
brcs PC+0x02
sbi DDRD, 0x02
ldi b, 0x3c ;28 ; 30us @ 4MHz
irq0_2:
dec b
brne irq0_2
cbi DDRD, 0x02
ldi b, (1<<INT0)
out GIFR, b
dec txbcnt
brne irq0_exit
adiw ZL, 0x01
cpi ZL, low(code * 0x02) + 0x08
breq irq0_4
lpm
mov shift, r0
ldi txbcnt, 0x08

irq0_exit:
ldi b, (1<<TOIE0)
out TIFR, b
out TIMSK, b
ldi b, 0xf4 ; ~720us @ 4MHz
out TCNT0, b
out SREG, sreg
reti

irq0_4:
ldi shift, 0x80
andi flags, ~((1<<RXD)+(1<<MODE))
rjmp irq0_exit

tim0_ovf:
in sreg, SREG
ldi b, 0x00
out TIMSK, b
cbi DDRD, 0x02
tim0_ovf0:
sbis PIND, 0x02
rjmp tim0_ovf0
ldi b, 0x35 ; 40us @ 4MHz
tim0_ovf1:
dec b
brne tim0_ovf1
sbi DDRD, 0x02
ldi b, 0xc8 ; 150us @ 4MHz
tim0_ovf2:
dec b
brne tim0_ovf2
cbi DDRD, 0x02
ldi b, (1<<INT0)
out GIFR, b
ldi shift, 0x80
andi flags, ~((1<<RXD)+(1<<MODE))
out SREG, sreg
reti

;*******************************************************************************

code:
.db 0x01, 0x35
.db 0xb1, 0x87
.db 0x09, 0x00
.db 0x00, 0x68

;******** Revision *************************************************************

.org FLASHEND

rev:
.dw 0x0000