Почему вместо синуса вижу корявый меандр?
Не реагирует на изменение амплитуды сигнала.
С какой стороны младшие биты? (c D0 или с D6)
Тактирую ПЛИС по CLK_OUT от АЦП
АЦП ADS6145
http://www.ti.com/lit/ds/symlink/ads6145.pdf
Спасибо.
Код
component IBUFGDS
-- -- synopsys translate_off
generic( DIFF_TERM : boolean := FALSE);
-- -- synopsys translate_on
port ( I : in std_logic;
IB : in std_logic;
O : out std_logic);
end component;
attribute IOSTANDARD of IBUFGDS : component is "DEFAULT";
attribute DIFF_TERM of IBUFGDS : component is "FALSE";
attribute BOX_TYPE of IBUFGDS : component is "BLACK_BOX";
component IBUFDS
-- synopsys translate_off
generic( DIFF_TERM : boolean := FALSE);
-- synopsys translate_on
port ( I : in std_logic;
IB : in std_logic;
O : out std_logic);
end component;
attribute IOSTANDARD of IBUFDS : component is "DEFAULT";
attribute DIFF_TERM of IBUFDS : component is "FALSE";
attribute BOX_TYPE of IBUFDS : component is "BLACK_BOX";
begin
data_out <= out13 & out12 & out11 & out10 & out9 & out8 & out7 & out6 & out5 &
out4 & out3 & out2 & out1 & out0 ;
clk_out <= USER_CLK;
IBUFGDS_1 : IBUFGDS
port map (I=>SMA_DIFF_CLK_IN_P,
IB=>SMA_DIFF_CLK_IN_N,
O=>USER_CLK);
IBUFDS_1 : IBUFDS
port map (I=>HDR2_28_SM_11_P,
IB=>HDR2_26_SM_11_N,
O=>DDR_1);
IBUFDS_2 : IBUFDS
port map (I=>HDR2_32_DIFF_3_P,
IB=>HDR2_30_DIFF_3_N,
O=>DDR_2);
....
process(USER_CLK)
begin
if (USER_CLK = '1') then
out0 <= DDR_0;
out2 <= DDR_1;
out4 <= DDR_2;
out6 <= DDR_3;
out8 <= DDR_4;
out10<= DDR_5;
out12<= DDR_6;
elsif (USER_CLK = '0') then
out1 <= DDR_0;
out3 <= DDR_1;
out5 <= DDR_2;
out7 <= DDR_3;
out9 <= DDR_4;
out11 <= DDR_5;
out13 <= DDR_6;
end if;
end process;
-- -- synopsys translate_off
generic( DIFF_TERM : boolean := FALSE);
-- -- synopsys translate_on
port ( I : in std_logic;
IB : in std_logic;
O : out std_logic);
end component;
attribute IOSTANDARD of IBUFGDS : component is "DEFAULT";
attribute DIFF_TERM of IBUFGDS : component is "FALSE";
attribute BOX_TYPE of IBUFGDS : component is "BLACK_BOX";
component IBUFDS
-- synopsys translate_off
generic( DIFF_TERM : boolean := FALSE);
-- synopsys translate_on
port ( I : in std_logic;
IB : in std_logic;
O : out std_logic);
end component;
attribute IOSTANDARD of IBUFDS : component is "DEFAULT";
attribute DIFF_TERM of IBUFDS : component is "FALSE";
attribute BOX_TYPE of IBUFDS : component is "BLACK_BOX";
begin
data_out <= out13 & out12 & out11 & out10 & out9 & out8 & out7 & out6 & out5 &
out4 & out3 & out2 & out1 & out0 ;
clk_out <= USER_CLK;
IBUFGDS_1 : IBUFGDS
port map (I=>SMA_DIFF_CLK_IN_P,
IB=>SMA_DIFF_CLK_IN_N,
O=>USER_CLK);
IBUFDS_1 : IBUFDS
port map (I=>HDR2_28_SM_11_P,
IB=>HDR2_26_SM_11_N,
O=>DDR_1);
IBUFDS_2 : IBUFDS
port map (I=>HDR2_32_DIFF_3_P,
IB=>HDR2_30_DIFF_3_N,
O=>DDR_2);
....
process(USER_CLK)
begin
if (USER_CLK = '1') then
out0 <= DDR_0;
out2 <= DDR_1;
out4 <= DDR_2;
out6 <= DDR_3;
out8 <= DDR_4;
out10<= DDR_5;
out12<= DDR_6;
elsif (USER_CLK = '0') then
out1 <= DDR_0;
out3 <= DDR_1;
out5 <= DDR_2;
out7 <= DDR_3;
out9 <= DDR_4;
out11 <= DDR_5;
out13 <= DDR_6;
end if;
end process;
