......
ram RAMin(.clock_a(CLOCK_25),         .clock_b(CLOCK_50i),
                  .address_a(w_address_in), .address_b(w_address_in_nios),

              .data_a(w_data_in), .data_b(),
              .q_a(),                    .q_b(w_data_in_nios),
            
             .rden_a(1'b0), .rden_b(1'b1),            
             .wren_a(1'b1), .wren_b(1'b0));
            
  ram RAMout(.clock_a(CLOCK_25),        .clock_b(CLOCK_50i),
                 .address_a(w_address_out), .address_b(w_address_out_nios),
                
              .data_a(),             .data_b(w_data_out_nios),
          .q_a(w_data_out), .q_b(),

              .rden_a(1'b1),  .rden_b(1'b0),
                  .wren_a(1'b0),  .wren_b(1'b1));            
            
    de0_nano_Qsys d1(
        .clk_clk(CLOCK_50i),                // clk.clk
        .reset_reset_n(1'b1),                 // reset.reset_n
        .sdra_wire_addr(DRAM_ADDR),   // new_sdram_controller_wire.addr
        .sdra_wire_ba(DRAM_BA),       // .ba
        .sdra_wire_cas_n(DRAM_CAS_N), // .cas_n
        .sdra_wire_cke(DRAM_CKE),     // .cke
        .sdra_wire_cs_n(DRAM_CS_N),   // .cs_n
        .sdra_wire_dq(DRAM_DQ),       // .dq
        .sdra_wire_dqm(DRAM_DQM),     // .dqm
        .sdra_wire_ras_n(DRAM_RAS_N), // .ras_n
        .sdra_wire_we_n(DRAM_WE_N),   // .we_n
        
        .addres_nios_in_export(w_address_in_nios),  //  addres_nios_in.export
        .data_nios_in_export(w_data_in_nios),    //    data_nios_in.export
        
        .addres_nios_out_export(w_address_out_nios), // addres_nios_out.export
                .data_nios_out_export(w_data_out_nios),   //   data_nios_out.export      
             
                .signal_nios_in_export({w_data_ready,w_data_ready_FS}),  //  signal_nios_in.export
                .signal_nios_out_export({w_data_ready_PE,reset}),  // signal_nios_out.export
      
                .uart_0_rxd(RxD),      //    uart_0.rxd
                .uart_0_txd(TxD),       //   uart_0.txd      
    );

  ...
   IOWR_ALTERA_AVALON_PIO_DATA(ADDRES_NIOS_IN_BASE, 0x00);
   aM[1][0].p_int = IORD_ALTERA_AVALON_PIO_DATA(DATA_NIOS_IN_BASE);
  ...

  .....

  assign w_data_in    = r_data_in;
  assign w_address_in = r_address_in;

  if(count == 4110) begin        
    r_data_in    <= out_conv;    
    r_address_in <= 0;
    r_conv       <= {{3'b001},{54'b0}};
  end else;
    
   if(count == 4120) begin
        r_data_in      <= out_conv;            
    r_address_in <= 1;
    r_conv          <= {{4'b0001},{53'b0}};
   end else;

   ....

avalon_bridge_waitrequest      : in  std_logic;
avalon_bridge_readdata         : in  std_logic_vector(31 downto 0);
avalon_bridge_readdatavalid    : in  std_logic;
avalon_bridge_burstcount       : out std_logic_vector(0 downto 0);
avalon_bridge_writedata        : out std_logic_vector(31 downto 0);
avalon_bridge_address          : out std_logic_vector(15 downto 0);
avalon_bridge_write            : out std_logic;
avalon_bridge_read             : out std_logic;
avalon_bridge_byteenable       : out std_logic_vector(3 downto 0);
avalon_bridge_debugaccess      : out std_logic;

IOWR(AVALON_BRIDGE_BASE, addr, wr_dat);
rd_dat = IORD(AVALON_BRIDGE_BASE, addr);