void write_rf_settings(int SPIx, int direct)
{
    if(direct == 1)//tx
    {
        uint8_t PA_TABLE[8] = {0x00,0x12,0x0e,0x34,0x60,0xc5,0xc1,0xc0};

        write_reg(SPIx, IOCFG0,0x06);  //GDO0 Output Pin Configuration
        write_reg(SPIx, FIFOTHR,0x47); //RX FIFO and TX FIFO Thresholds
        write_reg(SPIx, PKTCTRL0,0x05);//Packet Automation Control
        write_reg(SPIx, CHANNR,0x01);  //Channel Number
        write_reg(SPIx, FSCTRL1,0x06); //Frequency Synthesizer Control
        write_reg(SPIx, FREQ2,0x10);   //Frequency Control Word, High Byte
        write_reg(SPIx, FREQ1,0xB1);   //Frequency Control Word, Middle Byte
        write_reg(SPIx, FREQ0,0x3B);   //Frequency Control Word, Low Byte
        write_reg(SPIx, MDMCFG4,0xF6); //Modem Configuration
        write_reg(SPIx, MDMCFG3,0x83); //Modem Configuration
        write_reg(SPIx, MDMCFG2,0x13); //Modem Configuration
        write_reg(SPIx, DEVIATN,0x15); //Modem Deviation Setting
        write_reg(SPIx, MCSM0,0x18);   //Main Radio Control State Machine Configuration
        write_reg(SPIx, FOCCFG,0x16);  //Frequency Offset Compensation Configuration
        write_reg(SPIx, WORCTRL,0xFB); //Wake On Radio Control
        write_reg(SPIx, FREND0,0x17);  //Front End TX Configuration
        write_reg(SPIx, FSCAL3,0xE9);  //Frequency Synthesizer Calibration
        write_reg(SPIx, FSCAL2,0x2A);  //Frequency Synthesizer Calibration
        write_reg(SPIx, FSCAL1,0x00);  //Frequency Synthesizer Calibration
        write_reg(SPIx, FSCAL0,0x1F);  //Frequency Synthesizer Calibration
        write_reg(SPIx, TEST2,0x81);   //Various Test Settings
        write_reg(SPIx, TEST1,0x35);   //Various Test Settings
        write_reg(SPIx, TEST0,0x09);   //Various Test Settings

        write_burst_reg(SPIx, PATABLE, PA_TABLE, 8);
    }
    if(direct == 0)//rx
    {
        uint8_t PA_TABLE[8] = {0x00,0x12,0x0e,0x34,0x60,0xc5,0xc1,0xc0};

        write_reg(SPIx, IOCFG0,0x07);  //GDO0 Output Pin Configuration
        write_reg(SPIx, FIFOTHR,0x47); //RX FIFO and TX FIFO Thresholds
        write_reg(SPIx, PKTCTRL0,0x05);//Packet Automation Control
        write_reg(SPIx, CHANNR,0x01);  //Channel Number
        write_reg(SPIx, FSCTRL1,0x06); //Frequency Synthesizer Control
        write_reg(SPIx, FREQ2,0x10);   //Frequency Control Word, High Byte
        write_reg(SPIx, FREQ1,0xB1);   //Frequency Control Word, Middle Byte
        write_reg(SPIx, FREQ0,0x3B);   //Frequency Control Word, Low Byte
        write_reg(SPIx, MDMCFG4,0xF6); //Modem Configuration
        write_reg(SPIx, MDMCFG3,0x83); //Modem Configuration
        write_reg(SPIx, MDMCFG2,0x13); //Modem Configuration
        write_reg(SPIx, DEVIATN,0x15); //Modem Deviation Setting
        write_reg(SPIx, MCSM0,0x18);   //Main Radio Control State Machine Configuration
        write_reg(SPIx, FOCCFG,0x16);  //Frequency Offset Compensation Configuration
        write_reg(SPIx, WORCTRL,0xFB); //Wake On Radio Control
        write_reg(SPIx, FREND0,0x17);  //Front End TX Configuration
        write_reg(SPIx, FSCAL3,0xE9);  //Frequency Synthesizer Calibration
        write_reg(SPIx, FSCAL2,0x2A);  //Frequency Synthesizer Calibration
        write_reg(SPIx, FSCAL1,0x00);  //Frequency Synthesizer Calibration
        write_reg(SPIx, FSCAL0,0x1F);  //Frequency Synthesizer Calibration
        write_reg(SPIx, TEST2,0x81);   //Various Test Settings
        write_reg(SPIx, TEST1,0x35);   //Various Test Settings
        write_reg(SPIx, TEST0,0x09);   //Various Test Settings

        write_burst_reg(SPIx, PATABLE, PA_TABLE, 8);
    }
}