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Полная версия этой страницы: Схема тактирования всех MCB Spartan-6 от одного тактового источника
Форум разработчиков электроники ELECTRONIX.ru > Программируемая логика ПЛИС (FPGA,CPLD, PLD) > Работаем с ПЛИС, области применения, выбор
ZZZRF413
Jan 27 2015, 13:41
Всем доброго дня! sm.gif
Посоветуйте пожалуйста по следующему вопросу. Есть плата с Xilinx Spartan-6 FPGA (XC6SLX100T-3FGG676C). Необходимо задействовать все четыре Memory Controller Block от одного тактового сигнала. К 2 MCB подключена память DDR2 800 Mb/s (400 MHz), а к другим двум подключена память LPDDR 400 Mb/s (200 MHz). На ПЛИС заводиться тактовый сигнал 400 МГц.
В User guides я схемы не нашел. Там все просто: частота cX_sys_clk для каждого MCB (или группы из 2) заводиться "с улицы". В IP ядро соответственно встроен IBUFG. Опытным путем я пришел к следующей схеме:
1) Убрал из IP буфер IBUFG перед PLL
2) Подал входную частоту на DCM_SP. Поскольку 400 МГц превышает максимальную входную частоту DCM пришлось задействовать параметр CLKIN_DIVIDE_BY_2. Получилась на выходе частота 200 МГц
3) C этого DCM_SP через BUFG подал частоту на два других DCM_SP, которые располагаются рядом с PLL. Соответственно с этих DCM_SP завел на соответствующий PLL.
4) Поскольку частота разные скорректировал для параметры IP для DDR2 (контроллеры C3 и C4).

Схема в приложении
Проект проходит P&R (трассируется), но по таймингам не проходит(см. приложение). В проекте контроллер LPDDR (контроллеры C5 и C1) не задействован, синтезируется только схема калибровки.
Если DCM_SP не ставить проект не проходит P&R (не трассируется).

Собственно вопрос как побороть эту проблему?
Я вот думаю у меня задан тайминг на входную тактовую частоту, а для остальных ISE сам прописывает. Может там что-нибудь не так и на самом деле все ок? Мне бы не хотелось бы гонятся за черной кошкой в черной комнате...
Opex
Jan 27 2015, 15:59
Зачем такие сложности? Одна нужная частота сразу заводится, вторая делением на 2 получается. Поделить без DCM можно через BUFIO2.
Timmy
Jan 27 2015, 17:34
Судя по отчёту трассировщика, вы сконфигурировали MCB на 666МГц, но пытаетесь разгонять его до 800. Чтобы конфигурировать на 800, надо ставить галку "Use extended MCB perfomance range"(если эти условия на самом деле выполняютсяsm.gif).

И не понятно, зачем потребовались DCM. 100МГц для логики можно снять с одного из PLL, обслуживающих память, а 400МГц заводить на оба PLL прямо через BUFG.
ZZZRF413
Jan 28 2015, 07:19
Цитата(Opex @ Jan 27 2015, 18:59) *
Зачем такие сложности? Одна нужная частота сразу заводится, вторая делением на 2 получается. Поделить без DCM можно через BUFIO2.



Цитата(Timmy @ Jan 27 2015, 20:34) *
Судя по отчёту трассировщика, вы сконфигурировали MCB на 666МГц, но пытаетесь разгонять его до 800. Чтобы конфигурировать на 800, надо ставить галку "Use extended MCB perfomance range"(если эти условия на самом деле выполняютсяsm.gif).

И не понятно, зачем потребовались DCM. 100МГц для логики можно снять с одного из PLL, обслуживающих память, а 400МГц заводить на оба PLL прямо через BUFG.


Спасибо! Я разобрался почему проект не проходил P&R (не трассировался). Тактовый сигнал заводиться через IBUFGDS в банке 2. А я напрямую с него подавал на тактовый вход PLL находящиеся в других банка. Убрал DCM_SP и добавил BUFG после IBUFGDS и стал проходил P&R (трассироваться). Но проблемы с таймингами остались.

MCB я конфигурировал на 800 МГц. Галочку "Use extended MCB perfomance range" я поставил. На плате физически напряжение ядра 1,26 В. А как можно проверить сгенерировал ли MIG с учетом этой опции? В сгенерированых *.vhd файла есть информация об этом? Может быть ещё где-нибудь этот режим надо прописывать?
А ещё мне не нравиться то, что он ругается на тайминг TS_Memory_memc5_infrastructure*, который относится к контроллеру С5 памяти LPDDR работающей на 400 МГц...
Timmy
Jan 28 2015, 07:54
Цитата(ZZZRF413 @ Jan 28 2015, 10:19) *
MCB я конфигурировал на 800 МГц. Галочку "Use extended MCB perfomance range" я поставил. На плате физически напряжение ядра 1,26 В. А как можно проверить сгенерировал ли MIG с учетом этой опции? В сгенерированых *.vhd файла есть информация об этом? Может быть ещё где-нибудь этот режим надо прописывать?
А ещё мне не нравиться то, что он ругается на тайминг TS_Memory_memc5_infrastructure*, который относится к контроллеру С5 памяти LPDDR работающей на 400 МГц...

Это надо посмотреть в сгенерированном UCF файле, лежащем в "user_design/par/". Возможно, вы на LPDDR контроллер подаёте в два раза большую частоту, чем он ждёт.
ZZZRF413
Jan 28 2015, 09:50
Цитата(Timmy @ Jan 28 2015, 11:54) *
Это надо посмотреть в сгенерированном UCF файле, лежащем в "user_design/par/". Возможно, вы на LPDDR контроллер подаёте в два раза большую частоту, чем он ждёт.


Посмотрел. В файле все ок. Режим стоит.
CODE
#######################################################################
#####
##
## Xilinx, Inc. 2006 www.xilinx.com
## Пн 26. янв 13:41:05 2015
## Generated by MIG Version 3.6.1
##
############################################################################
## File name : DDR_Memory.ucf
##
## Details : Constraints file
## FPGA family: spartan6
## FPGA: xc6slx100t-fgg676
## Speedgrade: -3
## Design Entry: VHDL
## Design: without Test bench
## DCM Used: Enable
## No.Of Memory Controllers: 4
##
############################################################################
############################################################################
# VCC AUX VOLTAGE
############################################################################
CONFIG VCCAUX=2.5; # Valid values are 2.5 and 3.3

############################################################################
# Extended MCB performance mode requires a different Vccint specification to
# achieve higher maximum frequencies for DDR2 and DDR3.Consult the Spartan-6
#datasheet (DS162) table 2 and 24 for more information
############################################################################
CONFIG MCB_PERFORMANCE= EXTENDED;


################################################################################
##
# Timing Ignore constraints for paths crossing the clock domain
################################################################################
##
NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "c?_pll_lock" TIG;


############################################################################
## Memory Controller 5
## Memory Device: LPDDR->MT46H128M16XXXX-5L-IT
## Frequency: 200 MHz
## Time Period: 5000 ps
## Supported Part Numbers: MT46H128M16LFCK-5L-IT
############################################################################

############################################################################
# All the IO resources in an IO tile which contains DQSP/UDQSP are used
# irrespective of a single-ended or differential DQS design. Any signal that
# is connected to the free pin of the same IO tile in a single-ended design
# will be unrouted. Hence, the IOB cannot used as general pupose IO.
############################################################################
CONFIG PROHIBIT = F26,M26;

############################################################################
## Clock constraints
############################################################################
NET "memc5_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK5";
TIMESPEC "TS_SYS_CLK5" = PERIOD "SYS_CLK5" 5 ns HIGH 50 %;
############################################################################

############################################################################
# I/O STANDARDS
############################################################################

NET "mcb5_dram_dq[*]" IOSTANDARD = MOBILE_DDR;
NET "mcb5_dram_a[*]" IOSTANDARD = MOBILE_DDR;
NET "mcb5_dram_ba[*]" IOSTANDARD = MOBILE_DDR;
NET "mcb5_dram_dqs" IOSTANDARD = MOBILE_DDR;
NET "mcb5_dram_udqs" IOSTANDARD = MOBILE_DDR;
NET "mcb5_dram_ck" IOSTANDARD = DIFF_MOBILE_DDR;
NET "mcb5_dram_ck_n" IOSTANDARD = DIFF_MOBILE_DDR;
NET "mcb5_dram_cke" IOSTANDARD = MOBILE_DDR;
NET "mcb5_dram_ras_n" IOSTANDARD = MOBILE_DDR;
NET "mcb5_dram_cas_n" IOSTANDARD = MOBILE_DDR;
NET "mcb5_dram_we_n" IOSTANDARD = MOBILE_DDR;
NET "mcb5_dram_dm" IOSTANDARD = MOBILE_DDR;
NET "mcb5_dram_udm" IOSTANDARD = MOBILE_DDR;
NET "mcb5_rzq" IOSTANDARD = MOBILE_DDR;
NET "c5_sys_clk" IOSTANDARD = LVCMOS25;
NET "c5_sys_rst_n" IOSTANDARD = LVCMOS18;
############################################################################
# MCB 5
# Pin Location Constraints for Clock, Masks, Address, and Controls
############################################################################

NET "mcb5_dram_a[0]" LOC = "C25";
NET "mcb5_dram_a[10]" LOC = "F22";
NET "mcb5_dram_a[11]" LOC = "K19";
NET "mcb5_dram_a[12]" LOC = "C24";
NET "mcb5_dram_a[13]" LOC = "B24";
NET "mcb5_dram_a[1]" LOC = "C26";
NET "mcb5_dram_a[2]" LOC = "E24";
NET "mcb5_dram_a[3]" LOC = "K21";
NET "mcb5_dram_a[4]" LOC = "G23";
NET "mcb5_dram_a[5]" LOC = "M18";
NET "mcb5_dram_a[6]" LOC = "M19";
NET "mcb5_dram_a[7]" LOC = "E23";
NET "mcb5_dram_a[8]" LOC = "H21";
NET "mcb5_dram_a[9]" LOC = "H22";
NET "mcb5_dram_ba[0]" LOC = "L19";
NET "mcb5_dram_ba[1]" LOC = "K20";
NET "mcb5_dram_cas_n" LOC = "G24";
NET "mcb5_dram_ck" LOC = "B25";
NET "mcb5_dram_ck_n" LOC = "B26";
NET "mcb5_dram_cke" LOC = "D23";
NET "mcb5_dram_dm" LOC = "J24";
NET "mcb5_dram_dq[0]" LOC = "G25";
NET "mcb5_dram_dq[10]" LOC = "J25";
NET "mcb5_dram_dq[11]" LOC = "J26";
NET "mcb5_dram_dq[12]" LOC = "L25";
NET "mcb5_dram_dq[13]" LOC = "L26";
NET "mcb5_dram_dq[14]" LOC = "N25";
NET "mcb5_dram_dq[15]" LOC = "N26";
NET "mcb5_dram_dq[1]" LOC = "G26";
NET "mcb5_dram_dq[2]" LOC = "H24";
NET "mcb5_dram_dq[3]" LOC = "H26";
NET "mcb5_dram_dq[4]" LOC = "E25";
NET "mcb5_dram_dq[5]" LOC = "E26";
NET "mcb5_dram_dq[6]" LOC = "D24";
NET "mcb5_dram_dq[7]" LOC = "D26";
NET "mcb5_dram_dq[8]" LOC = "K24";
NET "mcb5_dram_dq[9]" LOC = "K26";
NET "mcb5_dram_dqs" LOC = "F24";
NET "mcb5_dram_ras_n" LOC = "F23";
NET "c5_sys_clk" LOC = "C13";
NET "c5_sys_rst_n" LOC = "J15";
NET "mcb5_dram_udm" LOC = "J23";
NET "mcb5_dram_udqs" LOC = "M24";
NET "mcb5_dram_we_n" LOC = "J20";

################################################################################
##
#RZQ is required for all MCB designs. Do not move the location #
#of this pin for ES devices.For production devices, RZQ can be moved to any #
#valid package pin within the MCB bank.For designs using Calibrated Input Termination, #
#a 2R resistor should be connected between RZQand ground, where R is the desired#
#input termination value. Otherwise, RZQ should be left as a no-connect (NC) pin.#
################################################################################
##
NET "mcb5_rzq" LOC = "H20";

############################################################################
## Memory Controller 1
## Memory Device: LPDDR->MT46H128M16XXXX-5L-IT
## Frequency: 200 MHz
## Time Period: 5000 ps
## Supported Part Numbers: MT46H128M16LFCK-5L-IT
############################################################################

############################################################################
# All the IO resources in an IO tile which contains DQSP/UDQSP are used
# irrespective of a single-ended or differential DQS design. Any signal that
# is connected to the free pin of the same IO tile in a single-ended design
# will be unrouted. Hence, the IOB cannot used as general pupose IO.
############################################################################
CONFIG PROHIBIT = V26,AC26;

############################################################################
# I/O STANDARDS
############################################################################

NET "mcb1_dram_dq[*]" IOSTANDARD = MOBILE_DDR;
NET "mcb1_dram_a[*]" IOSTANDARD = MOBILE_DDR;
NET "mcb1_dram_ba[*]" IOSTANDARD = MOBILE_DDR;
NET "mcb1_dram_dqs" IOSTANDARD = MOBILE_DDR;
NET "mcb1_dram_udqs" IOSTANDARD = MOBILE_DDR;
NET "mcb1_dram_ck" IOSTANDARD = DIFF_MOBILE_DDR;
NET "mcb1_dram_ck_n" IOSTANDARD = DIFF_MOBILE_DDR;
NET "mcb1_dram_cke" IOSTANDARD = MOBILE_DDR;
NET "mcb1_dram_ras_n" IOSTANDARD = MOBILE_DDR;
NET "mcb1_dram_cas_n" IOSTANDARD = MOBILE_DDR;
NET "mcb1_dram_we_n" IOSTANDARD = MOBILE_DDR;
NET "mcb1_dram_dm" IOSTANDARD = MOBILE_DDR;
NET "mcb1_dram_udm" IOSTANDARD = MOBILE_DDR;
NET "mcb1_rzq" IOSTANDARD = MOBILE_DDR;
############################################################################
# MCB 1
# Pin Location Constraints for Clock, Masks, Address, and Controls
############################################################################

NET "mcb1_dram_a[0]" LOC = "P24";
NET "mcb1_dram_a[10]" LOC = "N23";
NET "mcb1_dram_a[11]" LOC = "N20";
NET "mcb1_dram_a[12]" LOC = "N22";
NET "mcb1_dram_a[13]" LOC = "L23";
NET "mcb1_dram_a[1]" LOC = "P26";
NET "mcb1_dram_a[2]" LOC = "P22";
NET "mcb1_dram_a[3]" LOC = "T22";
NET "mcb1_dram_a[4]" LOC = "N24";
NET "mcb1_dram_a[5]" LOC = "U23";
NET "mcb1_dram_a[6]" LOC = "U24";
NET "mcb1_dram_a[7]" LOC = "P21";
NET "mcb1_dram_a[8]" LOC = "P17";
NET "mcb1_dram_a[9]" LOC = "P19";
NET "mcb1_dram_ba[0]" LOC = "R20";
NET "mcb1_dram_ba[1]" LOC = "R21";
NET "mcb1_dram_cas_n" LOC = "R26";
NET "mcb1_dram_ck" LOC = "R23";
NET "mcb1_dram_ck_n" LOC = "R24";
NET "mcb1_dram_cke" LOC = "N21";
NET "mcb1_dram_dm" LOC = "W24";
NET "mcb1_dram_dq[0]" LOC = "AA25";
NET "mcb1_dram_dq[10]" LOC = "AB24";
NET "mcb1_dram_dq[11]" LOC = "AB26";
NET "mcb1_dram_dq[12]" LOC = "Y24";
NET "mcb1_dram_dq[13]" LOC = "Y26";
NET "mcb1_dram_dq[14]" LOC = "AE25";
NET "mcb1_dram_dq[15]" LOC = "AE26";
NET "mcb1_dram_dq[1]" LOC = "AA26";
NET "mcb1_dram_dq[2]" LOC = "W25";
NET "mcb1_dram_dq[3]" LOC = "W26";
NET "mcb1_dram_dq[4]" LOC = "U25";
NET "mcb1_dram_dq[5]" LOC = "U26";
NET "mcb1_dram_dq[6]" LOC = "T24";
NET "mcb1_dram_dq[7]" LOC = "T26";
NET "mcb1_dram_dq[8]" LOC = "AD24";
NET "mcb1_dram_dq[9]" LOC = "AD26";
NET "mcb1_dram_dqs" LOC = "V24";
NET "mcb1_dram_ras_n" LOC = "R25";
NET "mcb1_dram_udm" LOC = "V23";
NET "mcb1_dram_udqs" LOC = "AC25";
NET "mcb1_dram_we_n" LOC = "R18";

################################################################################
##
#RZQ is required for all MCB designs. Do not move the location #
#of this pin for ES devices.For production devices, RZQ can be moved to any #
#valid package pin within the MCB bank.For designs using Calibrated Input Termination, #
#a 2R resistor should be connected between RZQand ground, where R is the desired#
#input termination value. Otherwise, RZQ should be left as a no-connect (NC) pin.#
################################################################################
##
NET "mcb1_rzq" LOC = "N17";


NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train" TIG; ## This path exists for DDR2 only

############################################################################
## Memory Controller 3
## Memory Device: DDR2_SDRAM->MT47H64M16XX-25
## Frequency: 400 MHz
## Time Period: 2500 ps
## Supported Part Numbers: MT47H64M16HR-25
############################################################################

############################################################################
## Clock constraints
############################################################################
NET "memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK3";
#TIMESPEC "TS_SYS_CLK3" = PERIOD "SYS_CLK3" 2.5 ns HIGH 50 %;
TIMESPEC "TS_SYS_CLK3" = PERIOD "SYS_CLK3" 5 ns HIGH 50 %;
############################################################################

############################################################################
## I/O TERMINATION
############################################################################
NET "mcb3_dram_dq[*]" IN_TERM = NONE;
NET "mcb3_dram_dqs" IN_TERM = NONE;
NET "mcb3_dram_dqs_n" IN_TERM = NONE;
NET "mcb3_dram_udqs" IN_TERM = NONE;
NET "mcb3_dram_udqs_n" IN_TERM = NONE;

############################################################################
# I/O STANDARDS
############################################################################

NET "mcb3_dram_dq[*]" IOSTANDARD = SSTL18_II;
NET "mcb3_dram_a[*]" IOSTANDARD = SSTL18_II;
NET "mcb3_dram_ba[*]" IOSTANDARD = SSTL18_II;
NET "mcb3_dram_dqs" IOSTANDARD = DIFF_SSTL18_II;
NET "mcb3_dram_udqs" IOSTANDARD = DIFF_SSTL18_II;
NET "mcb3_dram_dqs_n" IOSTANDARD = DIFF_SSTL18_II;
NET "mcb3_dram_udqs_n" IOSTANDARD = DIFF_SSTL18_II;
NET "mcb3_dram_ck" IOSTANDARD = DIFF_SSTL18_II;
NET "mcb3_dram_ck_n" IOSTANDARD = DIFF_SSTL18_II;
NET "mcb3_dram_cke" IOSTANDARD = SSTL18_II;
NET "mcb3_dram_ras_n" IOSTANDARD = SSTL18_II;
NET "mcb3_dram_cas_n" IOSTANDARD = SSTL18_II;
NET "mcb3_dram_we_n" IOSTANDARD = SSTL18_II;
NET "mcb3_dram_odt" IOSTANDARD = SSTL18_II;
NET "mcb3_dram_dm" IOSTANDARD = SSTL18_II;
NET "mcb3_dram_udm" IOSTANDARD = SSTL18_II;
NET "mcb3_rzq" IOSTANDARD = SSTL18_II;
NET "mcb3_zio" IOSTANDARD = SSTL18_II;
NET "c3_sys_clk" IOSTANDARD = LVCMOS25;
NET "c3_sys_rst_n" IOSTANDARD = LVCMOS18;
############################################################################
# MCB 3
# Pin Location Constraints for Clock, Masks, Address, and Controls
############################################################################

NET "mcb3_dram_a[0]" LOC = "R10";
NET "mcb3_dram_a[10]" LOC = "N8";
NET "mcb3_dram_a[11]" LOC = "N4";
NET "mcb3_dram_a[12]" LOC = "P8";
NET "mcb3_dram_a[1]" LOC = "T9";
NET "mcb3_dram_a[2]" LOC = "P6";
NET "mcb3_dram_a[3]" LOC = "R8";
NET "mcb3_dram_a[4]" LOC = "N7";
NET "mcb3_dram_a[5]" LOC = "R2";
NET "mcb3_dram_a[6]" LOC = "R1";
NET "mcb3_dram_a[7]" LOC = "N6";
NET "mcb3_dram_a[8]" LOC = "R4";
NET "mcb3_dram_a[9]" LOC = "R3";
NET "mcb3_dram_ba[0]" LOC = "P3";
NET "mcb3_dram_ba[1]" LOC = "P1";
NET "mcb3_dram_ba[2]" LOC = "R5";
NET "mcb3_dram_cas_n" LOC = "R6";
NET "mcb3_dram_ck" LOC = "U5";
NET "mcb3_dram_ck_n" LOC = "T4";
NET "mcb3_dram_cke" LOC = "R9";
NET "mcb3_dram_dm" LOC = "W3";
NET "mcb3_dram_dq[0]" LOC = "Y3";
NET "mcb3_dram_dq[10]" LOC = "AE2";
NET "mcb3_dram_dq[11]" LOC = "AE1";
NET "mcb3_dram_dq[12]" LOC = "AD3";
NET "mcb3_dram_dq[13]" LOC = "AD1";
NET "mcb3_dram_dq[14]" LOC = "AB3";
NET "mcb3_dram_dq[15]" LOC = "AB1";
NET "mcb3_dram_dq[1]" LOC = "Y1";
NET "mcb3_dram_dq[2]" LOC = "W2";
NET "mcb3_dram_dq[3]" LOC = "W1";
NET "mcb3_dram_dq[4]" LOC = "T3";
NET "mcb3_dram_dq[5]" LOC = "T1";
NET "mcb3_dram_dq[6]" LOC = "U2";
NET "mcb3_dram_dq[7]" LOC = "U1";
NET "mcb3_dram_dq[8]" LOC = "AA2";
NET "mcb3_dram_dq[9]" LOC = "AA1";
NET "mcb3_dram_dqs" LOC = "V3";
NET "mcb3_dram_dqs_n" LOC = "V1";
NET "mcb3_dram_odt" LOC = "T8";
NET "mcb3_dram_ras_n" LOC = "R7";
NET "c3_sys_clk" LOC = "AE15";
NET "c3_sys_rst_n" LOC = "Y12";
NET "mcb3_dram_udm" LOC = "V4";
NET "mcb3_dram_udqs" LOC = "AC2";
NET "mcb3_dram_udqs_n" LOC = "AC1";
NET "mcb3_dram_we_n" LOC = "P5";

################################################################################
##
#RZQ is required for all MCB designs. Do not move the location #
#of this pin for ES devices.For production devices, RZQ can be moved to any #
#valid package pin within the MCB bank.For designs using Calibrated Input Termination, #
#a 2R resistor should be connected between RZQand ground, where R is the desired#
#input termination value. Otherwise, RZQ should be left as a no-connect (NC) pin.#
################################################################################
##
NET "mcb3_rzq" LOC = "AB5";
################################################################################
##
#ZIO is only required for MCB designs using Calibrated Input Termination.#
#ZIO can be moved to any valid package pin (i.e. bonded IO) within the#
#MCB bank but must be left as a no-connect (NC) pin.#
################################################################################
##
NET "mcb3_zio" LOC = "AA4";

############################################################################
## Memory Controller 4
## Memory Device: DDR2_SDRAM->MT47H64M16XX-25
## Frequency: 400 MHz
## Time Period: 2500 ps
## Supported Part Numbers: MT47H64M16HR-25
############################################################################

############################################################################
## I/O TERMINATION
############################################################################
NET "mcb4_dram_dq[*]" IN_TERM = NONE;
NET "mcb4_dram_dqs" IN_TERM = NONE;
NET "mcb4_dram_dqs_n" IN_TERM = NONE;
NET "mcb4_dram_udqs" IN_TERM = NONE;
NET "mcb4_dram_udqs_n" IN_TERM = NONE;

############################################################################
# I/O STANDARDS
############################################################################

NET "mcb4_dram_dq[*]" IOSTANDARD = SSTL18_II;
NET "mcb4_dram_a[*]" IOSTANDARD = SSTL18_II;
NET "mcb4_dram_ba[*]" IOSTANDARD = SSTL18_II;
NET "mcb4_dram_dqs" IOSTANDARD = DIFF_SSTL18_II;
NET "mcb4_dram_udqs" IOSTANDARD = DIFF_SSTL18_II;
NET "mcb4_dram_dqs_n" IOSTANDARD = DIFF_SSTL18_II;
NET "mcb4_dram_udqs_n" IOSTANDARD = DIFF_SSTL18_II;
NET "mcb4_dram_ck" IOSTANDARD = DIFF_SSTL18_II;
NET "mcb4_dram_ck_n" IOSTANDARD = DIFF_SSTL18_II;
NET "mcb4_dram_cke" IOSTANDARD = SSTL18_II;
NET "mcb4_dram_ras_n" IOSTANDARD = SSTL18_II;
NET "mcb4_dram_cas_n" IOSTANDARD = SSTL18_II;
NET "mcb4_dram_we_n" IOSTANDARD = SSTL18_II;
NET "mcb4_dram_odt" IOSTANDARD = SSTL18_II;
NET "mcb4_dram_dm" IOSTANDARD = SSTL18_II;
NET "mcb4_dram_udm" IOSTANDARD = SSTL18_II;
NET "mcb4_rzq" IOSTANDARD = SSTL18_II;
NET "mcb4_zio" IOSTANDARD = SSTL18_II;
############################################################################
# MCB 4
# Pin Location Constraints for Clock, Masks, Address, and Controls
############################################################################

NET "mcb4_dram_a[0]" LOC = "L7";
NET "mcb4_dram_a[10]" LOC = "J9";
NET "mcb4_dram_a[11]" LOC = "E3";
NET "mcb4_dram_a[12]" LOC = "K8";
NET "mcb4_dram_a[1]" LOC = "L6";
NET "mcb4_dram_a[2]" LOC = "K10";
NET "mcb4_dram_a[3]" LOC = "M8";
NET "mcb4_dram_a[4]" LOC = "J7";
NET "mcb4_dram_a[5]" LOC = "L4";
NET "mcb4_dram_a[6]" LOC = "L3";
NET "mcb4_dram_a[7]" LOC = "L10";
NET "mcb4_dram_a[8]" LOC = "C2";
NET "mcb4_dram_a[9]" LOC = "C1";
NET "mcb4_dram_ba[0]" LOC = "B2";
NET "mcb4_dram_ba[1]" LOC = "B1";
NET "mcb4_dram_ba[2]" LOC = "G3";
NET "mcb4_dram_cas_n" LOC = "L8";
NET "mcb4_dram_ck" LOC = "K5";
NET "mcb4_dram_ck_n" LOC = "J5";
NET "mcb4_dram_cke" LOC = "K9";
NET "mcb4_dram_dm" LOC = "J3";
NET "mcb4_dram_dq[0]" LOC = "H3";
NET "mcb4_dram_dq[10]" LOC = "K3";
NET "mcb4_dram_dq[11]" LOC = "K1";
NET "mcb4_dram_dq[12]" LOC = "M3";
NET "mcb4_dram_dq[13]" LOC = "M1";
NET "mcb4_dram_dq[14]" LOC = "N2";
NET "mcb4_dram_dq[15]" LOC = "N1";
NET "mcb4_dram_dq[1]" LOC = "H1";
NET "mcb4_dram_dq[2]" LOC = "G2";
NET "mcb4_dram_dq[3]" LOC = "G1";
NET "mcb4_dram_dq[4]" LOC = "D3";
NET "mcb4_dram_dq[5]" LOC = "D1";
NET "mcb4_dram_dq[6]" LOC = "E2";
NET "mcb4_dram_dq[7]" LOC = "E1";
NET "mcb4_dram_dq[8]" LOC = "J2";
NET "mcb4_dram_dq[9]" LOC = "J1";
NET "mcb4_dram_dqs" LOC = "F3";
NET "mcb4_dram_dqs_n" LOC = "F1";
NET "mcb4_dram_odt" LOC = "M6";
NET "mcb4_dram_ras_n" LOC = "L9";
NET "mcb4_dram_udm" LOC = "J4";
NET "mcb4_dram_udqs" LOC = "L2";
NET "mcb4_dram_udqs_n" LOC = "L1";
NET "mcb4_dram_we_n" LOC = "G4";

################################################################################
##
#RZQ is required for all MCB designs. Do not move the location #
#of this pin for ES devices.For production devices, RZQ can be moved to any #
#valid package pin within the MCB bank.For designs using Calibrated Input Termination, #
#a 2R resistor should be connected between RZQand ground, where R is the desired#
#input termination value. Otherwise, RZQ should be left as a no-connect (NC) pin.#
################################################################################
##
NET "mcb4_rzq" LOC = "M4";
################################################################################
##
#ZIO is only required for MCB designs using Calibrated Input Termination.#
#ZIO can be moved to any valid package pin (i.e. bonded IO) within the#
#MCB bank but must be left as a no-connect (NC) pin.#
################################################################################
##
NET "mcb4_zio" LOC = "H6";


Я сделал деление на 2 входной частоты через BUFIO. На вход PLL, отвечающему за LPDDR идет 200 МГц. И все равно ругается на тайминги (в приложении). А для DDR2 так же идет 200 МГц, но я там в настройках PLL задаю значение CLKFBOUT_MULT в два раза больше чем было, т.к. входная частота на PLL меньше в два раза указаной при генерировании IP (400 МГц).
Timmy
Jan 28 2015, 10:39
Цитата(ZZZRF413 @ Jan 28 2015, 12:50) *
Я сделал деление на 2 входной частоты через BUFIO. На вход PLL, отвечающему за LPDDR идет 200 МГц. И все равно ругается на тайминги (в приложении). А для DDR2 так же идет 200 МГц, но я там в настройках PLL задаю значение CLKFBOUT_MULT в два раза больше чем было, т.к. входная частота на PLL меньше в два раза указаной при генерировании IP (400 МГц).

Это уже совсем другая ошибка. Причиной, видимо, является слишком высокая частота калибровки(mcb_drp_clk).
ZZZRF413
Jan 28 2015, 16:41
Цитата(Timmy @ Jan 28 2015, 14:39) *
Это уже совсем другая ошибка. Причиной, видимо, является слишком высокая частота калибровки(mcb_drp_clk).


Попробовал уменьшить mcb_drp_clk путем увеличения коэффициента деления CLKOUT3_DIVIDE на соответствующем выводе PLL. Не помогло.
Что ещё можно попробовать?
Timmy
Jan 28 2015, 17:59
Цитата(ZZZRF413 @ Jan 28 2015, 19:41) *
Попробовал уменьшить mcb_drp_clk путем увеличения коэффициента деления CLKOUT3_DIVIDE на соответствующем выводе PLL. Не помогло.
Что ещё можно попробовать?

Хотя нет, это не из-за высокой частоты mcb_drp_clk, путь же между разными клок доменами. Там по идее должен быть сделан FALSE PATH.
ZZZRF413
Jan 29 2015, 07:34
Добавил в свой .ucf из IP-шного:
CONFIG MCB_PERFORMANCE= EXTENDED;
Стало лучше, теперь только 3 вместо 6 (см. приложение)

Мой .ucf
CODE

# Clock signals
NET "clk" LOC = AC14 |IOSTANDARD = LVCMOS33;

NET "CLK" TNM_NET = "CLK";

#NET "clk0_n" LOC = AF15 | IOSTANDARD = LVPECL_33;
#NET "clk0_p" LOC = AE15 | IOSTANDARD = LVPECL_33;
NET "clk0_n" LOC = AF15 ;
NET "clk0_p" LOC = AE15 ;

# Controll signals
NET "RESET" LOC = AF4 |IOSTANDARD = LVCMOS33;
NET "Start" LOC = W7 |IOSTANDARD = LVCMOS33;
NET "Rev[0]" LOC = AA7 |IOSTANDARD = LVCMOS33;
NET "Rev[1]" LOC = AA6 |IOSTANDARD = LVCMOS33;
NET "Rev[2]" LOC = AF3 |IOSTANDARD = LVCMOS33;
# ADC signals
NET "ADC_SCLK" LOC = H12 |IOSTANDARD = LVCMOS18;
NET "ADC_SDIO" LOC = G13 |IOSTANDARD = LVCMOS18;
NET "ADC1_CSB" LOC = D21 |IOSTANDARD = LVCMOS18;
NET "ADC2_CSB" LOC = D22 |IOSTANDARD = LVCMOS18;
NET "ADC1_D_P[0]" LOC = H8 |IOSTANDARD = LVDS_25;
NET "ADC1_D_N[0]" LOC = G8 |IOSTANDARD = LVDS_25;
NET "ADC1_D_P[1]" LOC = F7 |IOSTANDARD = LVDS_25;
NET "ADC1_D_N[1]" LOC = F6 |IOSTANDARD = LVDS_25;
NET "ADC1_D_P[2]" LOC = C3 |IOSTANDARD = LVDS_25;
NET "ADC1_D_N[2]" LOC = B3 |IOSTANDARD = LVDS_25;
NET "ADC1_D_P[3]" LOC = G6 |IOSTANDARD = LVDS_25;
NET "ADC1_D_N[3]" LOC = F5 |IOSTANDARD = LVDS_25;
NET "ADC1_D_P[4]" LOC = E6 |IOSTANDARD = LVDS_25;
NET "ADC1_D_N[4]" LOC = E5 |IOSTANDARD = LVDS_25;
NET "ADC1_D_P[5]" LOC = H9 |IOSTANDARD = LVDS_25;
NET "ADC1_D_N[5]" LOC = G9 |IOSTANDARD = LVDS_25;
NET "ADC1_D_P[6]" LOC = A3 |IOSTANDARD = LVDS_25;
NET "ADC1_D_N[6]" LOC = A2 |IOSTANDARD = LVDS_25;
NET "ADC1_D_P[7]" LOC = F9 |IOSTANDARD = LVDS_25;
NET "ADC1_D_N[7]" LOC = E8 |IOSTANDARD = LVDS_25;
NET "ADC1_D_P[8]" LOC = D5 |IOSTANDARD = LVDS_25;
NET "ADC1_D_N[8]" LOC = C5 |IOSTANDARD = LVDS_25;
NET "ADC1_D_P[9]" LOC = H10 |IOSTANDARD = LVDS_25;
NET "ADC1_D_N[9]" LOC = G10 |IOSTANDARD = LVDS_25;
NET "ADC1_D_P[10]" LOC = B4 |IOSTANDARD = LVDS_25;
NET "ADC1_D_N[10]" LOC = A4 |IOSTANDARD = LVDS_25;
NET "ADC1_D_P[11]" LOC = F10 |IOSTANDARD = LVDS_25;
NET "ADC1_D_N[11]" LOC = E10 |IOSTANDARD = LVDS_25;
NET "ADC1_OR_P" LOC = B5 |IOSTANDARD = LVDS_25;
NET "ADC1_OR_N" LOC = A5 |IOSTANDARD = LVDS_25;
#NET "ADC1_DCO_P" LOC = J11 | IOSTANDARD = LVDS_25;
#NET "ADC1_DCO_N" LOC = G11 | IOSTANDARD = LVDS_25;
NET "ADC1_DCO_P" LOC = J11 |CLOCK_DEDICATED_ROUTE = FALSE;
NET "ADC1_DCO_N" LOC = G11 |CLOCK_DEDICATED_ROUTE = FALSE;

NET "ADC2_D_P[0]" LOC = K12 |IOSTANDARD = LVDS_25;
NET "ADC2_D_N[0]" LOC = J12 |IOSTANDARD = LVDS_25;
NET "ADC2_D_P[1]" LOC = J15 |IOSTANDARD = LVDS_25;
NET "ADC2_D_N[1]" LOC = H15 |IOSTANDARD = LVDS_25;
NET "ADC2_D_P[2]" LOC = J16 |IOSTANDARD = LVDS_25;
NET "ADC2_D_N[2]" LOC = J17 |IOSTANDARD = LVDS_25;
NET "ADC2_D_P[3]" LOC = F16 |IOSTANDARD = LVDS_25;
NET "ADC2_D_N[3]" LOC = E16 |IOSTANDARD = LVDS_25;
NET "ADC2_D_P[4]" LOC = G15 |IOSTANDARD = LVDS_25;
NET "ADC2_D_N[4]" LOC = F15 |IOSTANDARD = LVDS_25;
NET "ADC2_D_P[5]" LOC = F18 |IOSTANDARD = LVDS_25;
NET "ADC2_D_N[5]" LOC = E18 |IOSTANDARD = LVDS_25;
NET "ADC2_D_P[6]" LOC = G16 |IOSTANDARD = LVDS_25;
NET "ADC2_D_N[6]" LOC = F17 |IOSTANDARD = LVDS_25;
NET "ADC2_D_P[7]" LOC = F20 |IOSTANDARD = LVDS_25;
NET "ADC2_D_N[7]" LOC = E20 |IOSTANDARD = LVDS_25;
NET "ADC2_D_P[8]" LOC = H17 |IOSTANDARD = LVDS_25;
NET "ADC2_D_N[8]" LOC = G17 |IOSTANDARD = LVDS_25;
NET "ADC2_D_P[9]" LOC = C21 |IOSTANDARD = LVDS_25;
NET "ADC2_D_N[9]" LOC = B21 |IOSTANDARD = LVDS_25;
NET "ADC2_D_P[10]" LOC = H18 |IOSTANDARD = LVDS_25;
NET "ADC2_D_N[10]" LOC = H19 |IOSTANDARD = LVDS_25;
NET "ADC2_D_P[11]" LOC = B22 |IOSTANDARD = LVDS_25;
NET "ADC2_D_N[11]" LOC = A22 |IOSTANDARD = LVDS_25;
NET "ADC2_OR_P" LOC = G19 |IOSTANDARD = LVDS_25;
NET "ADC2_OR_N" LOC = F19 |IOSTANDARD = LVDS_25;
#NET "ADC2_DCO_P" LOC = B23 | IOSTANDARD = LVDS_25;
#NET "ADC2_DCO_N" LOC = A23 | IOSTANDARD = LVDS_25;
NET "ADC2_DCO_P" LOC = B23 |CLOCK_DEDICATED_ROUTE = FALSE;
NET "ADC2_DCO_N" LOC = A23 |CLOCK_DEDICATED_ROUTE = FALSE;
# Generator signals
NET "CLK_SCLK" LOC = AD6 |IOSTANDARD = LVCMOS33;
NET "CLK_CS" LOC = AF6 |IOSTANDARD = LVCMOS33;
#NET "CLK_SDO" LOC = W10 | IOSTANDARD = LVCMOS33;
NET "CLK_SDIO" LOC = W9 |IOSTANDARD = LVCMOS33;
# FPGA-DSP Signals
NET "UPP_CHA_WAIT" LOC = A13 |IOSTANDARD = LVCMOS18;
NET "UPP_CHA_ENABLE" LOC = C13 |IOSTANDARD = LVCMOS18;
NET "UPP_CHA_START" LOC = D13 |IOSTANDARD = LVCMOS18;
NET "UPP_CHA_CLK" LOC = E13 |IOSTANDARD = LVCMOS18;
NET "UPP_D[0]" LOC = Y6 |IOSTANDARD = LVCMOS18;
NET "UPP_D[1]" LOC = Y5 |IOSTANDARD = LVCMOS18;
NET "UPP_D[2]" LOC = AB4 |IOSTANDARD = LVCMOS18;
NET "UPP_D[3]" LOC = AC3 |IOSTANDARD = LVCMOS18;
NET "UPP_D[4]" LOC = V7 |IOSTANDARD = LVCMOS18;
NET "UPP_D[5]" LOC = V6 |IOSTANDARD = LVCMOS18;
NET "UPP_D[6]" LOC = U4 |IOSTANDARD = LVCMOS18;
NET "UPP_D[7]" LOC = U3 |IOSTANDARD = LVCMOS18;
NET "UPP_D[8]" LOC = U21 |IOSTANDARD = LVCMOS18;
NET "UPP_D[9]" LOC = T19 |IOSTANDARD = LVCMOS18;
NET "UPP_D[10]" LOC = T20 |IOSTANDARD = LVCMOS18;
NET "UPP_D[11]" LOC = AA23 |IOSTANDARD = LVCMOS18;
NET "UPP_D[12]" LOC = AA24 |IOSTANDARD = LVCMOS18;
NET "UPP_D[13]" LOC = U19 |IOSTANDARD = LVCMOS18;
NET "UPP_D[14]" LOC = U20 |IOSTANDARD = LVCMOS18;
NET "UPP_D[15]" LOC = V20 |IOSTANDARD = LVCMOS18;
NET "SPI0_CLK" LOC = AB14 |IOSTANDARD = LVCMOS33;
NET "UPP_Busy" LOC = AD4 |IOSTANDARD = LVCMOS33;
NET "SPI0_CS" LOC = W8 |IOSTANDARD = LVCMOS33;
NET "SPI0_EN" LOC = AD5 |IOSTANDARD = LVCMOS33;
NET "SPI0_SIMO" LOC = AC6 |IOSTANDARD = LVCMOS33;
NET "SPI0_SOMI" LOC = AC5 |IOSTANDARD = LVCMOS33;
# LPDDR signals
#CONFIG PROHIBIT = N17, H20;
NET "LPDDR1_DQ[0]" LOC = G25 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[1]" LOC = G26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[2]" LOC = H24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[3]" LOC = H26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[4]" LOC = E25 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[5]" LOC = E26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[6]" LOC = D24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[7]" LOC = D26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[8]" LOC = K24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[9]" LOC = K26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[10]" LOC = J25 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[11]" LOC = J26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[12]" LOC = L25 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[13]" LOC = L26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[14]" LOC = N25 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[15]" LOC = N26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_A[0]" LOC = C25 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_A[1]" LOC = C26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_A[2]" LOC = E24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_A[3]" LOC = K21 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_A[4]" LOC = G23 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_A[5]" LOC = M18 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_A[6]" LOC = M19 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_A[7]" LOC = E23 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_A[8]" LOC = H21 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_A[9]" LOC = H22 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_A[10]" LOC = F22 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_A[11]" LOC = K19 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_A[12]" LOC = C24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_A[13]" LOC = B24 | IOSTANDARD = MOBILE_DDR;
#NET "LPDDR1_BA0" LOC = L19 | IOSTANDARD = MOBILE_DDR;
#NET "LPDDR1_BA1" LOC = K20 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_BA[0]" LOC = L19 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_BA[1]" LOC = K20 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_LDM" LOC = J24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_UDM" LOC = J23 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_LDQS" LOC = F24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_UDQS" LOC = M24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_RAS" LOC = F23 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_CAS" LOC = G24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_WE" LOC = J20 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_CKE" LOC = D23 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_CK_P" LOC = B25 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "LPDDR1_CK_N" LOC = B26 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "LPDDR1_RZQ" LOC = H20 | IOSTANDARD = LVCMOS18;#| IOSTANDARD = DIFF_MOBILE_DDR;

NET "LPDDR2_DQ[0]" LOC = AA25 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[1]" LOC = AA26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[2]" LOC = W25 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[3]" LOC = W26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[4]" LOC = U25 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[5]" LOC = U26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[6]" LOC = T24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[7]" LOC = T26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[8]" LOC = AD24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[9]" LOC = AD26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[10]" LOC = AB24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[11]" LOC = AB26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[12]" LOC = Y24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[13]" LOC = Y26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[14]" LOC = AE25 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[15]" LOC = AE26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_A[0]" LOC = P24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_A[1]" LOC = P26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_A[2]" LOC = P22 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_A[3]" LOC = T22 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_A[4]" LOC = N24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_A[5]" LOC = U23 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_A[6]" LOC = U24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_A[7]" LOC = P21 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_A[8]" LOC = P17 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_A[9]" LOC = P19 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_A[10]" LOC = N23 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_A[11]" LOC = N20 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_A[12]" LOC = N22 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_A[13]" LOC = L23 | IOSTANDARD = MOBILE_DDR;
#NET "LPDDR2_BA0" LOC = R20 | IOSTANDARD = MOBILE_DDR;
#NET "LPDDR2_BA1" LOC = R21 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_BA[0]" LOC = R20 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_BA[1]" LOC = R21 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_LDM" LOC = W24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_UDM" LOC = V23 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_LDQS" LOC = V24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_UDQS" LOC = AC25 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_RAS" LOC = R25 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_CAS" LOC = R26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_WE" LOC = R18 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_CKE" LOC = N21 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_CK_P" LOC = R23 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "LPDDR2_CK_N" LOC = R24 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "LPDDR2_RZQ" LOC = N17 | IOSTANDARD = LVCMOS18;#| IOSTANDARD = DIFF_MOBILE_DDR;
# DDR2 signals
#CONFIG PROHIBIT = H6, AA4; # ZIO
NET "DDR21_DQ[0]" LOC = H3 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[1]" LOC = H1 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[2]" LOC = G2 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[3]" LOC = G1 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[4]" LOC = D3 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[5]" LOC = D1 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[6]" LOC = E2 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[7]" LOC = E1 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[8]" LOC = J2 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[9]" LOC = J1 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[10]" LOC = K3 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[11]" LOC = K1 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[12]" LOC = M3 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[13]" LOC = M1 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[14]" LOC = N2 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[15]" LOC = N1 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_A[0]" LOC = L7 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_A[1]" LOC = L6 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_A[2]" LOC = K10 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_A[3]" LOC = M8 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_A[4]" LOC = J7 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_A[5]" LOC = L4 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_A[6]" LOC = L3 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_A[7]" LOC = L10 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_A[8]" LOC = C2 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_A[9]" LOC = C1 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_A[10]" LOC = J9 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_A[11]" LOC = E3 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_A[12]" LOC = K8 | IOSTANDARD = MOBILE_DDR;
#NET "DDR21_BA0" LOC = B2 | IOSTANDARD = MOBILE_DDR;
#NET "DDR21_BA1" LOC = B1 | IOSTANDARD = MOBILE_DDR;
#NET "DDR21_BA2" LOC = G3 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_BA[0]" LOC = B2 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_BA[1]" LOC = B1 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_BA[2]" LOC = G3 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_LDM" LOC = J3 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_UDM" LOC = J4 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_LDQS_P" LOC = F3 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "DDR21_LDQS_N" LOC = F1 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "DDR21_UDQS_P" LOC = L2 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "DDR21_UDQS_N" LOC = L1 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "DDR21_RAS" LOC = L9 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_CAS" LOC = L8 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_WE" LOC = G4 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_CKE" LOC = K9 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_CK_P" LOC = K5 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "DDR21_CK_N" LOC = J5 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "DDR21_ODT" LOC = M6 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_ZIO" LOC = H6 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_RZQ" LOC = M4 | IOSTANDARD = LVCMOS18;#| IOSTANDARD = DIFF_MOBILE_DDR;

NET "DDR22_DQ[0]" LOC = Y3 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[1]" LOC = Y1 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[2]" LOC = W2 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[3]" LOC = W1 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[4]" LOC = T3 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[5]" LOC = T1 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[6]" LOC = U2 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[7]" LOC = U1 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[8]" LOC = AA2 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[9]" LOC = AA1 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[10]" LOC = AE2 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[11]" LOC = AE1 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[12]" LOC = AD3 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[13]" LOC = AD1 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[14]" LOC = AB3 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[15]" LOC = AB1 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_A[0]" LOC = R10 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_A[1]" LOC = T9 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_A[2]" LOC = P6 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_A[3]" LOC = R8 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_A[4]" LOC = N7 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_A[5]" LOC = R2 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_A[6]" LOC = R1 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_A[7]" LOC = N6 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_A[8]" LOC = R4 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_A[9]" LOC = R3 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_A[10]" LOC = N8 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_A[11]" LOC = N4 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_A[12]" LOC = P8 | IOSTANDARD = MOBILE_DDR;
#NET "DDR22_BA0" LOC = P3 | IOSTANDARD = MOBILE_DDR;
#NET "DDR22_BA1" LOC = P1 | IOSTANDARD = MOBILE_DDR;
#NET "DDR22_BA2" LOC = R5 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_BA[0]" LOC = P3 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_BA[1]" LOC = P1 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_BA[2]" LOC = R5 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_LDM" LOC = W3 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_UDM" LOC = V4 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_LDQS_P" LOC = V3 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "DDR22_LDQS_N" LOC = V1 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "DDR22_UDQS_P" LOC = AC2 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "DDR22_UDQS_N" LOC = AC1 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "DDR22_RAS" LOC = R7 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_CAS" LOC = R6 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_WE" LOC = P5 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_CKE" LOC = R9 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_CK_P" LOC = U5 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "DDR22_CK_N" LOC = T4 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "DDR22_ODT" LOC = T8 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_ZIO" LOC = AA4 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_RZQ" LOC = AB5 | IOSTANDARD = LVCMOS18;#| IOSTANDARD = DIFF_MOBILE_DDR;
# MRAM Signals
NET "MRAM_ADDRESS[0]" LOC = W16 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[1]" LOC = AB19 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[2]" LOC = AA19 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[3]" LOC = V16 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[4]" LOC = U15 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[5]" LOC = AA17 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[6]" LOC = Y17 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[7]" LOC = AB21 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[8]" LOC = AA21 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[9]" LOC = W18 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[10]" LOC = W17 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[11]" LOC = AF22 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[12]" LOC = W19 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[13]" LOC = V18 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[14]" LOC = AC22 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[15]" LOC = AB22 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[16]" LOC = Y20 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[17]" LOC = W20 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[18]" LOC = AF23 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[19]" LOC = AA22 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[0]" LOC = AB11 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[1]" LOC = AA10 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[2]" LOC = AB9 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[3]" LOC = AA9 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[4]" LOC = V10 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[5]" LOC = V11 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[6]" LOC = AA11 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[7]" LOC = Y11 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[8]" LOC = Y13 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[9]" LOC = W14 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[10]" LOC = AA12 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[11]" LOC = Y12 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[12]" LOC = AF14 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[13]" LOC = AD14 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[14]" LOC = AF13 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[15]" LOC = AE13 |IOSTANDARD = LVCMOS33;
NET "MRAM_E" LOC = Y16 |IOSTANDARD = LVCMOS33;
NET "MRAM_G" LOC = AA18 |IOSTANDARD = LVCMOS33;
NET "MRAM_LB" LOC = AB17 |IOSTANDARD = LVCMOS33;
NET "MRAM_UB" LOC = AA15 |IOSTANDARD = LVCMOS33;
NET "MRAM_W" LOC = AB15 |IOSTANDARD = LVCMOS33;
# LED
NET "LED<0>" LOC = L21 |IOSTANDARD = LVCMOS18;
NET "LED<1>" LOC = L20 |IOSTANDARD = LVCMOS18;
NET "LED<2>" LOC = M21 |IOSTANDARD = LVCMOS18;
NET "LED<3>" LOC = AA3 |IOSTANDARD = LVCMOS18;

NET "test<0>" LOC = G7 | IOSTANDARD = LVCMOS18;
NET "test<1>" LOC = H7 | IOSTANDARD = LVCMOS18;
NET "test<2>" LOC = B12 | IOSTANDARD = LVCMOS18;
NET "test<3>" LOC = A12 | IOSTANDARD = LVCMOS18;
NET "test<4>" LOC = B14 | IOSTANDARD = LVCMOS18;
NET "test<5>" LOC = A14 | IOSTANDARD = LVCMOS18;

CONFIG MCB_PERFORMANCE= EXTENDED;

#Created by Constraints Editor (xc6slx100t-fgg676-3) - 2014/12/25
NET "clk0_p" TNM_NET = clk0_p;
TIMESPEC TS_clk0_p = PERIOD "clk0_p" 2500 ps HIGH 50%;
NET "clk0_n" TNM_NET = clk0_n;
TIMESPEC TS_clk0_n = PERIOD "clk0_n" TS_clk0_p PHASE 1250 ps HIGH 50%;
#TIMESPEC TS_clk0_n = PERIOD "clk0_n" 5000 ps HIGH 50%;
NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 20 ns HIGH 50%;
#PIN "CLK_Module/CLK0PLL/PLL_ADV.CLKIN1" CLOCK_DEDICATED_ROUTE = FALSE;
#TIMESPEC TS_clk0_p = PERIOD "clk0_p" 5000 ps HIGH 50%;
#Created by Constraints Editor (xc6slx100t-fgg676-3) - 2014/12/25
#test 200
NET "ADC1_DCO_P" TNM_NET = ADC1_DCO_P;
TIMESPEC TS_ADC1_DCO_P = PERIOD "ADC1_DCO_P" 2500 ps HIGH 50%;
#TIMESPEC TS_ADC1_DCO_P = PERIOD "ADC1_DCO_P" 5000 ps HIGH 50%;
NET "ADC1_DCO_N" TNM_NET = ADC1_DCO_N;
TIMESPEC TS_ADC1_DCO_N = PERIOD "ADC1_DCO_N" TS_ADC1_DCO_P PHASE 1250 ps HIGH 50%;
#TIMESPEC TS_ADC1_DCO_N = PERIOD "ADC1_DCO_N" 2500 ps HIGH 50%;
#TIMESPEC TS_ADC1_DCO_N = PERIOD "ADC1_DCO_N" 5000 ps HIGH 50%;
NET "ADC2_DCO_N" TNM_NET = ADC2_DCO_N;
TIMESPEC TS_ADC2_DCO_N = PERIOD "ADC2_DCO_N" TS_ADC2_DCO_P PHASE 1250 ps HIGH 50%;
#TIMESPEC TS_ADC2_DCO_N = PERIOD "ADC2_DCO_N" 2500 ps HIGH 50%;
#TIMESPEC TS_ADC2_DCO_N = PERIOD "ADC2_DCO_N" 5000 ps HIGH 50%;
NET "ADC2_DCO_P" TNM_NET = ADC2_DCO_P;
TIMESPEC TS_ADC2_DCO_P = PERIOD "ADC2_DCO_P" 2500 ps HIGH 50%;
#TIMESPEC TS_ADC2_DCO_P = PERIOD "ADC2_DCO_P" 5000 ps HIGH 50%;
#test 200
Opex
Jan 29 2015, 08:37
Какие-то большие отклонения получаются от требуемых значений, и все межклоковые. Быть может, с фазами что-то? Или multicycle должны быть?

В ucf еще несколько клоков описывается. Если вход один - только его и нужно задавать, остальные должны сами средой считаться.



Timmy
Jan 29 2015, 09:22
Цитата(ZZZRF413 @ Jan 29 2015, 10:34) *
Добавил в свой .ucf из IP-шного:
CONFIG MCB_PERFORMANCE= EXTENDED;
Стало лучше, теперь только 3 вместо 6 (см. приложение)

IP-шный UCF у вас подключён? Там же стоят TIG вроде именно на те пути, где ошибки.
ZZZRF413
Jan 29 2015, 09:43
Все, я разобрался!
Необходимо вручную из файла .ucf IP ввести в свой проектный .ucf с указанием путей следующее:
Код
################################################################################
##
# Timing Ignore constraints for paths crossing the clock domain
################################################################################
##
NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "c?_pll_lock" TIG;


И в случае если используеться DDR2 ещё и это:
Код
NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train" TIG; ## This path exists for DDR2 only


Подобная тема так же обсуждалась тут: http://forums.xilinx.com/t5/MIG-Memory-Int.../highlight/true

Всем большое спасибо! sm.gif
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