#
NET "e0rx_clk" PERIOD = 40 ns;
OFFSET = IN 10 ns BEFORE "e0rx_clk";
NET "e0tx_clk" PERIOD = 40 ns;
OFFSET = OUT 20 ns AFTER "e0tx_clk";
OFFSET = IN 10 ns BEFORE "e0tx_clk";

NET "e0rx_clk" TNM_NET = "e0rx_clk";
NET "e0tx_clk" TNM_NET = "e0tx_clk";

TIMESPEC TS_erxclk = PERIOD "e0rx_clk" 36 ns;
TIMESPEC TS_etxclk = PERIOD "e0tx_clk" 36 ns;
#
OFFSET = IN 8 ns VALID 15 ns BEFORE "e0rx_clk";
OFFSET = OUT 15 ns AFTER "e0tx_clk";

# place a constraint on the LAN tx signals timing
NET "e0tx_clk" TNM = "LAN_TX_OUT";
#NET "TX_CTL" TNM = "LAN_TX_OUT";
NET "e0tx_en" TNM = "LAN_TX_OUT";
NET "e0tx_er" TNM = "LAN_TX_OUT";
NET "e0txd[0]" TNM = "LAN_TX_OUT";
NET "e0txd[1]" TNM = "LAN_TX_OUT";
NET "e0txd[2]" TNM = "LAN_TX_OUT";
NET "e0txd[3]" TNM = "LAN_TX_OUT";
NET "e0txd[4]" TNM = "LAN_TX_OUT";
NET "e0txd[5]" TNM = "LAN_TX_OUT";
NET "e0txd[6]" TNM = "LAN_TX_OUT";
NET "e0txd[7]" TNM = "LAN_TX_OUT";

TIMEGRP "LAN_TX_OUT" OFFSET = OUT 10.5 ns AFTER "e0rx_clk";

# In addition, place a constraint on the input pins from the PHY to minimize the delay spread among the rx pins
# place a constraint on the LAN rx signals timing
#NET "RX_CTL" TNM = "LAN_RX_IN";
NET "e0rx_er" TNM = "LAN_RX_IN";
NET "e0rxd[0]" TNM = "LAN_RX_IN";
NET "e0rxd[1]" TNM = "LAN_RX_IN";
NET "e0rxd[2]" TNM = "LAN_RX_IN";
NET "e0rxd[3]" TNM = "LAN_RX_IN";
NET "e0rxd[4]" TNM = "LAN_RX_IN";
NET "e0rxd[5]" TNM = "LAN_RX_IN";
NET "e0rxd[6]" TNM = "LAN_RX_IN";
NET "e0rxd[7]" TNM = "LAN_RX_IN";

TIMEGRP "LAN_RX_IN" OFFSET = IN 0.5 ns BEFORE "e0rx_clk";

Paths for end point e0txd<6> (V30.PAD), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths): -3.001ns (requirement - (clock arrival + clock path + data path + uncertainty))
Source: e0/Inst_Top_level_TCP/Inst_COM5401/IF_SEL_002.Inst_GMII_MII_WRAPPER/TXD_6 (FF)
Destination: e0txd<6> (PAD)
Source Clock: e0/Inst_Top_level_TCP/Inst_COM5401/TX_CLKG rising at 0.000ns
Requirement: 10.500ns
Data Path Delay: 4.111ns (Levels of Logic = 1)
Clock Path Delay: 9.365ns (Levels of Logic = 4)
Clock Uncertainty: 0.025ns

Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.050ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns

Maximum Clock Path at Slow Process Corner: e0rx_clk to e0/Inst_Top_level_TCP/Inst_COM5401/IF_SEL_002.Inst_GMII_MII_WRAPPER/TXD_6
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
W27.I Tiopi 1.557 e0rx_clk
e0rx_clk
clk_pad1/xcv2.u0/g0.ttl0.ip
ProtoComp1105.IMUX.23
BUFIO2_X4Y18.I net (fanout=1) 0.627 e0rx_clk_signal
BUFIO2_X4Y18.DIVCLK Tbufcko_DIVCLK 0.190 e0/Inst_Top_level_TCP/Inst_COM5401/IF_SEL_002.Inst_GMII_MII_WRAPPER/BUFIO2_inst
e0/Inst_Top_level_TCP/Inst_COM5401/IF_SEL_002.Inst_GMII_MII_WRAPPER/BUFIO2_inst
BUFGMUX_X2Y3.I0 net (fanout=1) 1.327 e0/Inst_Top_level_TCP/Inst_COM5401/IF_SEL_002.Inst_GMII_MII_WRAPPER/RX_CLK2
BUFGMUX_X2Y3.O Tgi0o 0.209 e0/Inst_Top_level_TCP/Inst_COM5401/IF_SEL_002.Inst_GMII_MII_WRAPPER/BUFG_001
e0/Inst_Top_level_TCP/Inst_COM5401/IF_SEL_002.Inst_GMII_MII_WRAPPER/BUFG_001
BUFGMUX_X3Y5.I1 net (fanout=62) 2.826 e0/Inst_Top_level_TCP/Inst_COM5401/RX_CLKG
BUFGMUX_X3Y5.O Tgi1o 0.209 e0/Inst_Top_level_TCP/Inst_COM5401/IF_SEL_002.Inst_GMII_MII_WRAPPER/BUFGMUX_inst
e0/Inst_Top_level_TCP/Inst_COM5401/IF_SEL_002.Inst_GMII_MII_WRAPPER/BUFGMUX_inst
OLOGIC_X35Y94.CLK0 net (fanout=85) 2.420 e0/Inst_Top_level_TCP/Inst_COM5401/TX_CLKG
------------------------------------------------- ---------------------------
Total 9.365ns (2.165ns logic, 7.200ns route)
(23.1% logic, 76.9% route)

Maximum Data Path at Slow Process Corner: e0/Inst_Top_level_TCP/Inst_COM5401/IF_SEL_002.Inst_GMII_MII_WRAPPER/TXD_6 to e0txd<6>
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
OLOGIC_X35Y94.OQ Tockq 1.080 e0/Inst_Top_level_TCP/Inst_COM5401/IF_SEL_002.Inst_GMII_MII_WRAPPER/TXD<6>
e0/Inst_Top_level_TCP/Inst_COM5401/IF_SEL_002.Inst_GMII_MII_WRAPPER/TXD_6
V30.O net (fanout=1) 0.309 e0/Inst_Top_level_TCP/Inst_COM5401/IF_SEL_002.Inst_GMII_MII_WRAPPER/TXD<6>
V30.PAD Tioop 2.722 e0txd<6>
e0txd_6_OBUF
e0txd<6>
------------------------------------------------- ---------------------------
Total 4.111ns (3.802ns logic, 0.309ns route)
(92.5% logic, 7.5% route)

--------------------------------------------------------------------------------

-- two cases: @1000 Mbps (GMII), the GTX_CLK is an output . At 10/100Mbps (MII), the TX_CLK in an input.

-- In the 1000Mbps mode, we must provide a 125 MHz GTX_CLK to the PHY. Make tx clock <= rx clock frequency.
-- In the 10/100 Mbps mode, the TX_CLKG clock is generated by the PHY (may drift w.r.t rx clock frequency)
-- IMPORTANT Key design assumption: PHY always generates a RX_CLK, even when no cable is connected.

BUFGMUX_inst : BUFGMUX
generic map (
CLK_SEL_TYPE => "SYNC" -- Glitchless ("SYNC") or fast ("ASYNC") clock switch-over
)
port map (
O => TX_CLKG, -- 1-bit output: Clock buffer output
I0 => TX_CLK, -- 1-bit input: Clock buffer input (S=0)
I1 => RX_CLKG, -- 1-bit input: Clock buffer input (S=1)
S => GMII_FLAG -- 1-bit input: Clock buffer select
);

BUFIO2_inst : BUFIO2
generic map (
DIVIDE => 1, -- DIVCLK divider (1-8)
DIVIDE_BYPASS => TRUE, -- Bypass the divider circuitry (TRUE/FALSE)
I_INVERT => FALSE, -- Invert clock (TRUE/FALSE)
USE_DOUBLER => FALSE -- Use doubler circuitry (TRUE/FALSE)
)
port map (
DIVCLK => RX_CLK2, -- 1-bit output Divided clock output
IOCLK => open, -- 1-bit output I/O output clock
SERDESSTROBE => open, -- 1-bit output Output SERDES strobe (connect to ISERDES2/OSERDES2)
I => RX_CLK -- 1-bit input Clock input (connect to IBUFG)
);

-- declare the RX clock as a global clock
BUFG_001 : BUFG port map (
O => RX_CLKG, -- Clock buffer output
I => RX_CLK2 -- Clock buffer input
);

RX_CLKG <= RX_CLK;
TX_CLKG <= RX_CLKG;

NET "rgmii_rx_clk0" TNM_NET = "phy_clk_rx0";
TIMESPEC TS_phy_rx0 = PERIOD "phy_rx0" 8 ns HIGH 50 %;
///////////////////////////////////////////////////////
INST "rgmii_rxd0[0]" TNM = "rgmii_rx_d0_0";
INST "rgmii_rxd0[1]" TNM = "rgmii_rx_d0_1";
INST "rgmii_rxd0[2]" TNM = "rgmii_rx_d0_2";
INST "rgmii_rxd0[3]" TNM = "rgmii_rx_d0_3";
INST "rgmii_rx_ctl0" TNM = "rgmii_rx_ctrl0";
///////////////////////////////////////////////////////
TIMEGRP "rgmii_rx_d0_0" OFFSET = IN 0 ns VALID 3.5 ns BEFORE "rgmii_rx_clk0" RISING;
TIMEGRP "rgmii_rx_d0_0" OFFSET = IN 0 ns VALID 3.5 ns BEFORE "rgmii_rx_clk0" FALLING;

TIMEGRP "rgmii_rx_d0_1" OFFSET = IN 0 ns VALID 3.5 ns BEFORE "rgmii_rx_clk0" RISING;
TIMEGRP "rgmii_rx_d0_1" OFFSET = IN 0 ns VALID 3.5 ns BEFORE "rgmii_rx_clk0" FALLING;

TIMEGRP "rgmii_rx_d0_2" OFFSET = IN 0 ns VALID 3.5 ns BEFORE "rgmii_rx_clk0" RISING;
TIMEGRP "rgmii_rx_d0_2" OFFSET = IN 0 ns VALID 3.5 ns BEFORE "rgmii_rx_clk0" FALLING;

TIMEGRP "rgmii_rx_d0_3" OFFSET = IN 0 ns VALID 3.5 ns BEFORE "rgmii_rx_clk0" RISING;
TIMEGRP "rgmii_rx_d0_3" OFFSET = IN 0 ns VALID 3.5 ns BEFORE "rgmii_rx_clk0" FALLING;

TIMEGRP "rgmii_rx_ctrl0" OFFSET = IN 0 ns VALID 3.5 ns BEFORE "rgmii_rx_clk0" RISING;
TIMEGRP "rgmii_rx_ctrl0" OFFSET = IN 0 ns VALID 3.5 ns BEFORE "rgmii_rx_clk0" FALLING;

   (* IODELAY_GROUP = "group_1_0" *) // Specifies group name for associated IODELAYs and IDELAYCTRL
   IODELAY # (
      .DELAY_SRC("I"),  // Specify which input port to be used, "I"=IDATAIN,
                        //  "O"=ODATAIN, "DATAIN"=DATAIN, "IO"=Bi-directional
      .HIGH_PERFORMANCE_MODE("TRUE"), // "TRUE" specifies lower jitter
                                      //   at expense of more power
      .IDELAY_TYPE("FIXED"),  // "FIXED" or "VARIABLE"
      .IDELAY_VALUE(15),         // 0 to 63 tap values
      .ODELAY_VALUE(0),         // 0 to 63 tap values
      .REFCLK_FREQUENCY(200.0), // Frequency used for IDELAYCTRL
                                //   175.0 to 225.0
      .SIGNAL_PATTERN("DATA")  // Input signal type, "CLOCK" or "DATA"
   ) IODELAY_D0 (
      .DATAOUT(rgmii_rxd_delay[0]),   // 1-bit delayed data output
      .C(1'b0),     // 1-bit clock input
      .CE(1'b0),   // 1-bit clock enable input
      .DATAIN(1'b0),     // 1-bit internal data input
      .IDATAIN(rgmii_rxd[0]),   // 1-bit input data input (connect to port)
      .INC(1'b0), // 1-bit increment/decrement input
      .ODATAIN(),   // 1-bit output data input
      .RST(1'b0), // 1-bit active high, synch reset input
      .T(1'b0)      // 1-bit 3-state control input
   );

Slack (setup path):     0.987ns (requirement - (data path - clock path - clock arrival + uncertainty))
   Source:               rgmii_rxd0<0> (PAD)
   Destination:          RGMII_test/rgmii_0/IDDR_0 (FF)
   Destination Clock:    RGMII_test/rgmii_0/clk_out_iodelay rising at 0.000ns
   Requirement:          0.000ns
   Data Path Delay:      2.939ns (Levels of Logic = 2)
   Clock Path Delay:     3.951ns (Levels of Logic = 3)
   Clock Uncertainty:    0.025ns

RX_CLKG <= RX_CLK;
TX_CLKG <= RX_CLK;