void init_and_start_framebuffer(alt_sgdma_dev *dma)
{
    // frame buffer A
    alt_u8* buff;
    alt_u16 size;
    int i;

    for(i = 0; i < 3; ++i) {

    switch ( i ) {
            case 0:
                size = 0xa;
                buff = (alt_u8*)frameBufferA;
                break;
            case 1:
                size = 0x1;
                buff = (alt_u8*)frameBufferA + 0x10;
                break;
            case 2:
                size = 0x6400;
                buff = (alt_u8*)frameBufferA + 0x8 + 0x10;
                break;
        }

        alt_avalon_sgdma_construct_mem_to_stream_desc(
                                                        &dmaDescA[i],
                                                        (i<3) ? (&dmaDescA[i+1]) : &dmaDescEND,
                                                        (alt_u32*)buff,
                                                        size,
                                                        0,
                                                        i==0 | i==1, // sop
                                                        i==0 | i==2, // eop
                                                        0);

    }

int main()
{
    IOWR(frameBufferA, 0, 0x0a00000f);
    IOWR(frameBufferA+1, 0, 0x0a000000);
    IOWR(frameBufferA+2, 0, 0x00000200);
    IOWR(frameBufferA+3, 0, 0x00000000);

#include <stdio.h>
#include "sys/alt_stdio.h"
#include "io.h"
#include "system.h"
#include "unistd.h"
#include <math.h>
#include <altera_avalon_sgdma.h>
#include <altera_avalon_sgdma_descriptor.h>
#include <altera_avalon_sgdma_regs.h>


// DMA descriptors
alt_sgdma_descriptor* dmaDescA;
alt_sgdma_descriptor* dmaDescEND;

alt_sgdma_dev *dma; //DMA device

// we locate our first framebuffer at the beginning of the SDRAM
alt_u32* frameBufferA = (alt_u32*)ONCHIP_MEMORY2_0_BASE;


void my_dma_callback(void *data)
{
    // reset the OWNED_BY_HW bit in the descriptors to reuse the chain
    int i;
    for(i = 0; i < 3;++i)
        dmaDescA[i].control |= 1<<ALTERA_AVALON_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_OFST;

    // trigger another transfer all over again
    alt_avalon_sgdma_do_async_transfer((alt_sgdma_dev*)data, dmaDescA);
}



int main()
{
    dmaDescA = (alt_sgdma_descriptor*) ONCHIP_MEMORY2_BASE + 0xf00;
    dmaDescEND = (alt_sgdma_descriptor*) ONCHIP_MEMORY2_BASE;


    dma = alt_avalon_sgdma_open(SGDMA_0_NAME);


    // frame buffer
    alt_u8* buff;
    alt_u16 size;
    int i;

    for(i = 0; i < 3; ++i)
    {
    switch ( i ) {
            case 0:
                size = 0xa;
                buff = (alt_u8*)frameBufferA;
                break;
            case 1:
                size = 0x1;
                buff = (alt_u8*)frameBufferA;
                break;
            case 2:
                size = 0xff;
                buff = (alt_u8*)frameBufferA;
                break;
        }


        alt_avalon_sgdma_construct_mem_to_stream_desc(
                &dmaDescA[i],
                (i<3) ? (&dmaDescA[i+1]) : &dmaDescEND,
                (alt_u32*)buff,
                size,
                0,
                1, // sop
                1, // eop
                0);
    }



alt_avalon_sgdma_register_callback(
            dma, my_dma_callback,
            ALTERA_AVALON_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK
            |ALTERA_AVALON_SGDMA_CONTROL_IE_GLOBAL_MSK,
            (void*)dma);


    alt_avalon_sgdma_do_async_transfer(dma, dmaDescA);//start DMA transfer

;
return 0;
}