library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity clk_div7 is
Port ( clkin : in STD_LOGIC;
clkout : out STD_LOGIC);
end clk_div7;

architecture Behavioral of clk_div7 is
signal shift_reg : std_logic_vector(13 downto 0) := "00000001111111";
signal nclkin : std_logic := '1';
begin

nclkin <= not clkin;

process(clkin)
begin
if rising_edge(clkin) then
shift_reg <= shift_reg(11 downto 0) & shift_reg(13 downto 12);
end if;
end process;

ODDR2_inst : ODDR2
generic map(
DDR_ALIGNMENT => "C0", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => clkout, -- 1-bit output data
C0 => clkin, -- 1-bit clock input
C1 => nclkin, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => shift_reg(13), -- 1-bit data input (associated with C0)
D1 => shift_reg(12), -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);


end Behavioral;

module div7
(
input    clkin,
output     reg clkout
);
reg                reg1;
reg        [2:0]    reg2;

wire clk_w;
assign clk_w = reg1 ^ clkin;

always @ (posedge clk_w)
    begin
    reg1 <= clkin;
    if (reg2 == 6)
        begin
        reg2 <= 0;
        clkout <= ~clkout;
        end
    else    reg2 <= reg2 + 1;
    end
endmodule