struct otg_fs
{
struct global
{
uint32_t volatile GOTGCTL; // OTG control and status 0x000
uint32_t volatile GOTGINT; // OTG interrupt flags 0x004
uint32_t volatile GAHBCFG; // AHB configuration 0x008
uint32_t volatile GUSBCFG; // USB configuration 0x00C
uint32_t volatile GRSTCTL; // Core reset 0x010
uint32_t volatile GINTSTS; // Core interrupt flags 0x014
uint32_t volatile GINTMSK; // Core interrupt mask 0x018
uint32_t volatile GRXSTSR; // Receive status debug read 0x01C
uint32_t volatile GRXSTSP; // OTG status read and pop 0x020
uint32_t volatile GRXFSIZ; // Receive FIFO size 0x024
uint32_t volatile DIEPTXF0_HNPTXFSIZ; // Non periodic / EP0 Tx FIFO size 0x028
uint32_t volatile HNPTXSTS; // Non periodic Tx FIFO/queue status 0x02C
uint32_t reserved30[2]; // Reserved 0x030
uint32_t volatile GCCFG; // General core configuration 0x038
uint32_t volatile CID; // Product ID 0x03C
uint32_t reserved40[48]; // Reserved 0x040-0xFF
uint32_t volatile HPTXFSIZ; // Host periodic Tx FIFO size 0x100
uint32_t volatile DIEPTXF[3]; // Device IN endpoint Tx FIFO size 0x104
uint32_t reserved110[188]; // Reserved 0x110-0x3FF
};

struct host
{
uint32_t volatile HCFG; // Configuration 0x400
uint32_t volatile HFIR; // Frame interval 0x404
uint32_t volatile HFNUM; // Frame number/time remaining 0x408
uint32_t reserved40C; // Reserved 0x40C
uint32_t volatile HPTXSTS; // Periodic Tx FIFO / queue status 0x410
uint32_t volatile HAINT; // All channels interrupt flags 0x414
uint32_t volatile HAINTMSK; // All channels interrupt Mask 0x418
uint32_t reserved41C[9]; // Reserved 0x41C-0x43F
uint32_t volatile HPRT; // Port control and status 0x440
uint32_t reserved444[47]; // Reserved 0x444-0x4FF
struct
{
uint32_t volatile HCCHAR; // Characteristics 0x500, 0x520...0x5E0
uint32_t reserved504; // Reserved 0x504
uint32_t volatile HCINT; // Interrupt flags 0x508
uint32_t volatile HCINTMSK; // Interrupt mask 0x50C
uint32_t volatile HCTSIZ; // Transfer size 0x510
uint32_t reserved[3]; // Reserved 0x514-0x51F
} Channel[8];
uint32_t reserved600[128]; // Reserved 0x600-0x7FF
};

struct device
{
uint32_t volatile DCFG; // Configuration 0x800
uint32_t volatile DCTL; // Control 0x804
uint32_t volatile const DSTS; // Status 0x808
uint32_t reserved0C; // Reserved 0x80C
uint32_t volatile DIEPMSK; // IN endpoint interrupt mask 0x810
uint32_t volatile DOEPMSK; // OUT endpoint interrupt mask 0x814
uint32_t volatile DAINT; // All endpoints interrupt flags 0x818
uint32_t volatile DAINTMSK; // All endpoints interrupt mask 0x81C
uint32_t reserved820[2]; // Reserved 0x820-0x827
uint32_t volatile DVBUSDIS; // VBUS discharge time 0x828
uint32_t volatile DVBUSPULSE; // VBUS pulsing time 0x82C
uint32_t reserved830; // Reserved 0x830
uint32_t volatile DIEPEMPMSK; // IN endpoint FIFO empty mask 0x834
uint32_t reserved838[50]; // Reserved 0x838-0x8FF
struct in_ep
{
uint32_t volatile DIEPCTL; // Control 0x900, 0x920, 0x940, 0x960
uint32_t reserved904; // Reserved 0x904
uint32_t volatile DIEPINT; // Interrupt flags 0x908
uint32_t reserved90C; // Reserved 0x90C
uint32_t volatile DIEPTSIZ; // Transfer size 0x910
uint32_t reserved914; // Reserved 0x914
uint32_t volatile DTXFSTS; // Tx FIFO status 0x918
uint32_t reserved91C; // Reserved 0x91C
} IN_endpoint[4];
uint32_t reserved980[32 + 64]; // Reserved 0x980-0xAFF
struct out_ep
{
uint32_t volatile DOEPCTL; // Control 0xB00, 0xB20, 0xB40, 0xB60
uint32_t reservedB04; // Reserved 0xB04
uint32_t volatile DOEPINT; // Interrupt flags 0xB08
uint32_t reservedB0C; // Reserved 0xB0C
uint32_t volatile DOEPTSIZ; // Transfer size 0xB10
uint32_t reservedB14[3]; // Reserved 0xB14-0xB1F
} OUT_endpoint[4];
uint32_t reservedB80[32 + 128]; // Reserved 0xB80-0xDFF

struct generic_ep
{
uint32_t volatile CTL; // Control 0x00
uint32_t reserved04; // Reserved 0x04
uint32_t volatile INT; // Interrupt flags 0x08
uint32_t reserved0C; // Reserved 0x0C
uint32_t volatile TSIZ; // Transfer size 0x10
uint32_t reserved14[3]; // Reserved 0x14-0x1F
};
};

struct gating
{
uint32_t volatile PCGCR; // Power and clock gating 0xE00
uint32_t reservedE04[127]; // Reserved 0xE04-0xFFF
};

struct fifo
{
uint32_t volatile FIFO; // FIFO data 0x1000
uint32_t Reserved[1023]; // Reserved 0x1004-0x1FFF
};

struct rx_fifo : public fifo
{
public:
void * read(void * to, uint_fast16_t size);
};

struct tx_fifo : protected fifo
{
public:
void write(void const * from, uint_fast16_t size);
};

global Global;
host Host;
device Device;
gating Gating;
union
{
rx_fifo Rx_FIFO;
tx_fifo Tx_FIFO[8];
};
};