//ADC2_IN4 to DMA    
    RCC->APB2ENR |=RCC_APB2ENR_ADC2EN;                                            //
    ADC->CCR |= ADC_CCR_TSVREFE | ADC_CCR_ADCPRE;     
    ADC2->CR2 |= ADC_CR2_ADON;                                                            //ADON: A/D Converter ON    
    ADC2->CR2 |= ADC_CR2_DDS;                                                             //DMA: Direct memory access mode (for single ADC mode)
    ADC2->CR2 |= ADC_CR2_DMA;                                                             //DMA disable selection (for single ADC mode)
    ADC2->CR2 |= ADC_CR2_CONT;                                                            //CONT: Continuous conversion
    ADC2->SMPR2 |= ADC_SMPR2_SMP4_0;                                                 //IN4 = 001: 15 cycles
    ADC2->SQR1 &= ~(ADC_SQR1_L);                                                        //11: 1 conversions
    ADC2->SQR3 = 4;                                                                                    //
    
    RCC->AHB1ENR |=(1<<22);                                                      //DMA1EN: DMA2 clock enable
    DMA2_Stream2->CR |= DMA_SxCR_CHSEL_0;                          //001: channel 1 selected    
    DMA2_Stream2->CR |= (1<<13);                                        //MSIZE[1:0]: Memory data size 01: half-word (16-bit)
    DMA2_Stream2->CR |= (1<<11);                                          //PSIZE[1:0]: Peripheral data size 01: Half-word (16-bit)
    DMA2_Stream2->CR |= (1<<10);                                          //MINC: Memory increment mode
    DMA2_Stream2->CR |= DMA_SxCR_PL;
    DMA2_Stream2->CR &= ~((1<<7)|(1<<6));                       //DIR[1:0]: Data transfer direction 00: Peripheral-to-memory
    DMA2_Stream2->NDTR = sample_size_adc;                            //NDT[15:0]: Number of data items to transfer
    DMA2_Stream2->PAR = (uint32_t)&ADC2->DR;                  //PAR[31:0]: Peripheral address
    DMA2_Stream2->M0AR = (uint32_t)&massiv;                  //M0A[31:0]: Memory 0 address
    DMA2_Stream2->CR |= (1<<0);                                              //EN: Stream enable / flag stream ready when read low
    ADC2->CR2 |= ADC_CR2_SWSTART;                                            //SWSTART: Start conversion of regular channels

        DMA2_Stream2->CR &= ~DMA_SxCR_EN;
        DMA2_Stream2->M0AR = (uint32_t)&massiv;        
        DMA2_Stream2->NDTR = sample_size_adc; //NDT[15:0]: Number of data items to transfer
        DMA2->LIFCR |= ((1UL<<20)|(1<<21));
        ADC2->SR &= ~ADC_SR_OVR;
        ADC2->CR2 &= ~ADC_CR2_DMA;
        ADC2->CR2 |= ADC_CR2_DMA;
        DMA2_Stream2->CR |= DMA_SxCR_EN;//EN: Stream enable / flag stream ready when read low
        ADC2->CR2 |= ADC_CR2_SWSTART;