CBX_FILE=sp_mod_ram.vhd
CBX_HDL_LANGUAGE=VHDL
CBX_SINGLE_OUTPUT_FILE=ON
CBX_STRUCTURAL_NETLIST=OFF
INSTANCE_NAME="ram"
OPERATION_MODE=SINGLE_PORT
ENABLE_RUNTIME_MOD=YES
DEVICE_FAMILY="Cyclone III"
WIDTH_A=8 WIDTHAD_A=8 USE_WYS=ON
address_a clock0 data_a q_a rden_a wren_a

--synthesis_resources = M9K 1 sld_mod_ram_rom 1
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY sp_mod_ram IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock0 : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '1');
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rden_a : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '0'
);
END sp_mod_ram;

ARCHITECTURE RTL OF sp_mod_ram IS

ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
SIGNAL wire_altsyncram1_q_a : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_altsyncram1_q_b : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_mgl_prim2_address : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_mgl_prim2_data_write : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_mgl_prim2_enable_write : STD_LOGIC;
SIGNAL wire_mgl_prim2_tck_usr : STD_LOGIC;
COMPONENT sp_mod_ram_altsyncram_fuj1
PORT
(
address_a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '1');
clock0 : IN STD_LOGIC := '1';
clock1 : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '1');
data_b : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '1');
q_a : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
rden_a : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT sld_mod_ram_rom
GENERIC
(
CVALUE : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
IS_DATA_IN_RAM : NATURAL;
IS_READABLE : NATURAL;
NODE_NAME : NATURAL;
NUMWORDS : NATURAL;
SHIFT_COUNT_BITS : NATURAL;
WIDTH_WORD : NATURAL;
WIDTHAD : NATURAL
);
PORT
(
address : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
data_read : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
data_write : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
enable_write : OUT STD_LOGIC;
tck_usr : OUT STD_LOGIC
);
END COMPONENT;
BEGIN

q_a <= wire_altsyncram1_q_a;
altsyncram1 : sp_mod_ram_altsyncram_fuj1
PORT MAP (
address_a => address_a,
address_b => wire_mgl_prim2_address,
clock0 => clock0,
clock1 => wire_mgl_prim2_tck_usr,
data_a => data_a,
data_b => wire_mgl_prim2_data_write,
q_a => wire_altsyncram1_q_a,
q_b => wire_altsyncram1_q_b,
rden_a => rden_a,
wren_a => wren_a,
wren_b => wire_mgl_prim2_enable_write
);
mgl_prim2 : sld_mod_ram_rom
GENERIC MAP (
CVALUE => "00000000",
IS_DATA_IN_RAM => 1,
IS_READABLE => 1,
NODE_NAME => 1918987520,
NUMWORDS => 256,
SHIFT_COUNT_BITS => 4,
WIDTH_WORD => 8,
WIDTHAD => 8
)
PORT MAP (
address => wire_mgl_prim2_address,
data_read => wire_altsyncram1_q_b,
data_write => wire_mgl_prim2_data_write,
enable_write => wire_mgl_prim2_enable_write,
tck_usr => wire_mgl_prim2_tck_usr
);

END RTL; --sp_mod_ram
--VALID FILE