/* получение сигнала завершения конфигурации FPGA. Возврат: 0 - конфигурация не завершена */
static uint_fast8_t board_fpga_get_CONF_DONE(void)
{
    return (FPGA_CONF_DONE_INPUT & FPGA_CONF_DONE_BIT) != 0;

}

static uint_fast8_t board_fpga_get_NSTATUS(void)
{
    return (FPGA_NSTATUS_INPUT & FPGA_NSTATUS_BIT) != 0;

}


static void board_fpga_initialize(void)
{
    hardware_spi_master_setfreq(SPIC_SPEEDUFAST, SPISPEEDUFAST);
    HARDWARE_FPGA_LOADER_INITIALIZE();
}


/* FPGA загружается процессором с помощью SPI */
static void board_fpga_load_PS(void)
{
    #include "rbfimage_v3.h"

    //debug_printf_P(PSTR("fpga: board_fpga_load_PS start\n"));
    do {
        const size_t rbflength = sizeof rbfimage / sizeof rbfimage [0];
        /* After power up, the Cyclone IV device holds nSTATUS low during POR delay. */

        /* 1) Выставить "1" на nCONFIG */
        //debug_printf_P(PSTR("fpga: FPGA_NCONFIG_BIT=1\n"));
        FPGA_NCONFIG_PORT_C(FPGA_NCONFIG_BIT);
        /* x) Дождаться "0" на nSTATUS */
        //debug_printf_P(PSTR("fpga: waiting for FPGA_NSTATUS_BIT==0\n"));
        while (board_fpga_get_NSTATUS() != 0)
        ;
        FPGA_NCONFIG_PORT_S(FPGA_NCONFIG_BIT);
        /* 2) Дождаться "1" на nSTATUS */
        //debug_printf_P(PSTR("fpga: waiting for FPGA_NSTATUS_BIT==1\n"));
        while (board_fpga_get_NSTATUS() == 0)
    ;
        /* 3) Выдать байты (бладший бит .rbf файла первым) */
        //debug_printf_P(PSTR("fpga: start sending RBF image (%lu of 16-bit words)\n"), rbflength);
        if (rbflength != 0)
        {
            unsigned wcd = 0;
            size_t n = rbflength - 1;
            const uint16_t * p = rbfimage;
            //

            hardware_spi_connect_b16(SPIC_SPEEDUFAST, SPIC_MODE3);

            hardware_spi_b16_p1(* p ++);
            while (n --)
            {
                if (board_fpga_get_CONF_DONE() != 0)
                {
                    //debug_printf_P(PSTR("fpga: Unexpected state of CONF_DONE==1\n"));
                    break;
                }
                hardware_spi_b16_p2(* p ++);
            }

            //debug_printf_P(PSTR("fpga: done sending RBF image, waiting for CONF_DONE==1\n"));
            /* 4) Дождаться "1" на CONF_DONE */
            while (board_fpga_get_CONF_DONE() == 0)
            {
                ++ wcd;
                hardware_spi_b16_p2(0xffff);
            }

            hardware_spi_complete_b16();

            hardware_spi_disconnect();
            //debug_printf_P(PSTR("fpga: CONF_DONE asserted, wcd=%u\n"), wcd);
            /*
            After the configuration data is accepted and CONF_DONE goes
            high, Cyclone IV devices require 3,192 clock cycles to initialize properly and enter
            user mode.
            */
        }
    } while (board_fpga_get_NSTATUS() == 0);    // если ошибка - повторяем
    /* проверяем, проинициализировалась ли FPGA (вошла в user mode). */
    //while (HARDWARE_FPGA_IS_USER_MODE() == 0)
    //;
    local_delay_ms(400);
    //debug_printf_P(PSTR("fpga: board_fpga_load_PS done\n"));
}