HAL_ETH_ReadPHYRegister(&heth, 0x02, &high);
    HAL_ETH_ReadPHYRegister(&heth, 0x03, &low);

void init_ethernet (void)
{
/* Включаю тактирование на порты в.в. */
...

/* Initialize the ETH ethernet controller. */
U32 regv,tout,id1,id2,conn;
/* Enable System configuration controller clock */
RCC->APB2ENR |= (1 << 14);

/* Reset Ethernet MAC */
RCC->AHB1RSTR |= 0x02000000;

SYSCFG->PMC |= (1 << 23);

RCC->AHB1RSTR &= ~0x02000000;

RCC->AHB1ENR |= 0x1E000047;

/* Configure Port A ethernet pins (PA.1, PA.2, PA.7) */
GPIOA->MODER &= ~0x0000C03C;
GPIOA->MODER |= 0x00008028; /* Pins to alternate function */
GPIOA->OTYPER &= ~0x00000086; /* Pins in push-pull mode */
GPIOA->OSPEEDR |= 0x0000C03C; /* Slew rate as 100MHz pin */
GPIOA->PUPDR &= ~0x0000C03C; /* No pull up, no pull down */

GPIOA->AFR[0] &= ~0xF0000FF0;
GPIOA->AFR[0] |= 0xB0000BB0; /* Pins to AF11 (Ethernet) */

/* Configure Port C ethernet pins (PC.1, PC.4, PC.5) */
GPIOC->MODER &= ~0x00000F0C;
GPIOC->MODER |= 0x00000A08; /* Pins to alternate function */
GPIOC->OTYPER &= ~0x00000032; /* Pins in push-pull mode */
GPIOC->OSPEEDR |= 0x00000F0C; /* Slew rate as 100MHz pin */
GPIOC->PUPDR &= ~0x00000F0C; /* No pull up, no pull down */

GPIOC->AFR[0] &= ~0x00FF00F0;
GPIOC->AFR[0] |= 0x00BB00B0; /* Pins to AF11 (Ethernet) */

/* Configure Port B ethernet pins (PB.12, PB.13) */
GPIOB->MODER &= ~0x0F000000;
GPIOB->MODER |= 0x0A000000; /* Pin to alternate function */
GPIOB->OTYPER &= ~0x00003000; /* Pin in push-pull mode */
GPIOB->OSPEEDR |= 0x0F000000; /* Slew rate as 100MHz pin */
GPIOB->PUPDR &= ~0x0F000000; /* No pull up, no pull down */

GPIOB->AFR[1] &= ~0x00FF0000;
GPIOB->AFR[1] |= 0x00BB0000; /* Pin to AF11 (Ethernet) */

/* Configure Port B ethernet pins (PB.11) */
GPIOB->MODER &= ~0x00C00000;
GPIOB->MODER |= 0x00800000; /* Pins to alternate function */
GPIOB->OTYPER &= ~0x00000800; /* Pins in push-pull mode */
GPIOB->OSPEEDR |= 0x00C00000; /* Slew rate as 100MHz pin */
GPIOB->PUPDR &= ~0x0FF00000; /* No pull up, no pull down */

GPIOB->AFR[1] &= ~0x0000F000;
GPIOB->AFR[1] |= 0x0000B000; /* Pins to AF11 (Ethernet) */

ETH->DMABMR |= DBMR_SR;
while (ETH->DMABMR & DBMR_SR);
conn = 0;

/* HCLK Clock range 100-120MHz. */
ETH->MACMIIAR = 0x00000004;

/* Put the LAN8700 in reset mode */
write_PHY (PHY_REG_BCR, 0x8000);

/* Wait for hardware reset to end. */
for (tout = 0; tout < 0x100000; tout++)
{
regv = read_PHY (PHY_REG_BCR);
if (!(regv & 0x8000)) {
/* Reset complete */
break;
}
}

/* Check if this is a KSZ8863 PHY. */
id1 = read_PHY (PHY_REG_PID1);
id2 = read_PHY (PHY_REG_PID2);
if (((id1 << 16) | (id2 & 0xFFF0)) == 0x221430)
{
/* Use autonegotiation about the link speed. */
write_PHY (PHY_REG_BCR, PHY_AUTO_NEG);
/* Wait to complete Auto_Negotiation. */
for (tout = 0; tout < 0x100000; tout++) {
regv = read_PHY (PHY_REG_BSR);
if (regv & 0x0020) {
/* Autonegotiation Complete. */
break;
}
}
}

/* Check the link status. */
for (tout = 0; tout < 0x10000; tout++)
{
regv = read_PHY (PHY_REG_BSR);
if (regv & 0x0004)
{
conn |= PHY_CON_SET_FULLD;
/* Link is on. */
break;
}
}

/* Initialize MAC configuration register */
ETH->MACCR = MCR_ROD;

/* Configure Full/Half Duplex mode. */
if (regv & 0x0004)
{
/* Full duplex is enabled. */
conn |= PHY_CON_SET_FULLD;
}
else
{
/* Half duplex mode. */
}

/* Configure 100MBit/10MBit mode. */
if (regv & 0x0002)
{
/* 10MBit mode. */
}
else
{
/* 100MBit mode. */
conn |= PHY_CON_SET_100M;
}

/* Configure Full/Half Duplex mode. */
if (conn & PHY_CON_SET_FULLD) {
/* Full duplex is enabled. */
ETH->MACCR |= MCR_DM;
}

/* Configure 100MBit/10MBit mode. */
if (conn & PHY_CON_SET_100M) {
/* 100MBit mode. */
ETH->MACCR |= MCR_FES;
}

/* MAC address filtering, accept multicast packets. */
ETH->MACFFR = MFFR_HPF | MFFR_PAM;
ETH->MACFCR = MFCR_ZQPD;

/* Set the Ethernet MAC Address registers */
ETH->MACA0HR = ((U32)own_hw_adr[5] << 8) | (U32)own_hw_adr[4];
ETH->MACA0LR = ((U32)own_hw_adr[3] << 24) | (U32)own_hw_adr[2] << 16 |
((U32)own_hw_adr[1] << 8) | (U32)own_hw_adr[0];

/* Initialize Tx and Rx DMA Descriptors */
rx_descr_init ();
tx_descr_init ();

/* Flush FIFO, start DMA Tx and Rx */
ETH->DMAOMR = DOMR_FTF | DOMR_ST | DOMR_SR;

/* Enable receiver and transmiter */
ETH->MACCR |= MCR_TE | MCR_RE;

/* Reset all interrupts */
ETH->DMASR = 0xFFFFFFFF;

/* Enable Rx and Tx interrupts. */
ETH->DMAIER = ETH_DMAIER_NISE | ETH_DMAIER_AISE | ETH_DMAIER_RBUIE | ETH_DMAIER_RIE;

}