module root(
    input    rst,
    input    rst1
    input    main_clk,

    inout  [15:0]   sdram_ddr_dq,
    output [12:0]   sdram_ddr_a,
    output [1:0]    sdram_ddr_ba,
    output [0:0]    sdram_ddr_ck,
    output [0:0]    sdram_ddr_ck_n,
    output          sdram_ddr_cke,
    
    output          sdram_ddr_cs_n,
    output          sdram_ddr_ras_n,
    output          sdram_ddr_cas_n,
    output          sdram_ddr_we_n,
    inout  [1:0]    sdram_ddr_dqs,
    
    output          sdram_ddr_udm,
    output          sdram_ddr_ldm,
    
    output      led1
//    output      led2,
//    output      led3
);

mig_36_1 ddr_sdram
(
        .cntrl0_ddr_dq             (sdram_ddr_dq),
        .cntrl0_ddr_a              (sdram_ddr_a),
        .cntrl0_ddr_ba             (sdram_ddr_ba),
        .cntrl0_ddr_cke            (sdram_ddr_cke),
        .cntrl0_ddr_cs_n           (sdram_ddr_cs_n),
        .cntrl0_ddr_ras_n          (sdram_ddr_ras_n),
        .cntrl0_ddr_cas_n          (sdram_ddr_cas_n),
        .cntrl0_ddr_we_n           (sdram_ddr_we_n),
        .cntrl0_rst_dqs_div_in     (rst1),
        .cntrl0_rst_dqs_div_out    (sdram_rst_dqs_div_out),

        .reset_in_n                (rst),
        .cntrl0_burst_done         (sdram_burst_done),
        .cntrl0_init_val           (sdram_init_val),
        .cntrl0_ar_done            (sdram_ar_done),
        .cntrl0_user_data_valid    (sdram_user_data_valid),
        .cntrl0_auto_ref_req       (sdram_auto_ref_req),
    .cntrl0_user_command_register  (sdram_user_command_register),
        .cntrl0_user_cmd_ack       (sdram_user_cmd_ack),
        .cntrl0_clk_tb             (sdram_clk_tb),
        .cntrl0_clk90_tb           (sdram_clk90_tb),
        .cntrl0_sys_rst_tb         (sdram_sys_rst_tb),
        .cntrl0_sys_rst90_tb       (sdram_sys_rst90_tb),
        .cntrl0_sys_rst180_tb      (sdram_sys_rst180_tb),
        .cntrl0_user_output_data   (sdram_user_output_data),
        .cntrl0_user_input_data    (sdram_user_input_data),
        .cntrl0_user_input_address (sdram_user_input_address),

        .clk_int                   (clk0_buf),
        .clk90_int                 (clk90_buf),
        .dcm_lock                  (dcm1_lock),
        
        .cntrl0_ddr_dqs            (sdram_ddr_dqs),
        .cntrl0_ddr_ck             (sdram_ddr_ck),
        .cntrl0_ddr_ck_n           (sdram_ddr_ck_n)
);

  
    // user commands:                      
parameter  [2:0]  NOP_CMD        = 3'b000,
                    PRECHARGE_CMD  = 3'b001,
                    INIT_CMD       = 3'b010,
                    WRITE_CMD      = 3'b100,
                    READ_CMD       = 3'b110;

parameter  INIT                = 4'b0000,
             WAIT_INIT           = 4'b0001,
             READY               = 4'b0010,
             WAIT_WRITE          = 4'b0011,
             WRITE_a             = 4'b0100,
             WRITE_b             = 4'b0101,
             WRITE_c             = 4'b0110,
             READ_DATA           = 4'b0111;
            
            
    reg [3:0] state;
    reg [2:0]  user_command_r;
    reg [24:0] user_address_r;
    reg [15:0] user_outputData_r;
    reg [15:0] user_data_1_r;
    reg [15:0] user_inputData_r;
    
    reg [0:0]  led1_r;
    reg [0:0]  clk_3;
    reg [0:0] user_data_valid;
    
  

    assign sdram_user_command_register = user_command_r;
    assign sdram_user_input_address = user_address_r;
    assign sdram_user_output_data = user_outputData_r;
    assign sdram_user_input_data = user_inputData_r;
    //assign sdram_user_data_valid = user_data_valid;
  
              
    assign sdram_ddr_udm = 1'b1;
    assign sdram_ddr_ldm = 1'b1;
    assign led1 = led1_r;
    assign nclk = ~clk0_buf;    
    

     initial begin
         user_command_r = NOP_CMD;
         //user_burst_done_r <= 1'b0;
         state = INIT;
     end
    
       always @ (negedge clk0_buf) begin
         case (state)
           INIT:
            begin
               led1_r = 1'b0;
               user_command_r <= INIT_CMD;
               state <= WAIT_INIT;
            end
    
           WAIT_INIT:
             begin
               if (sdram_user_cmd_ack == 1'b0) begin
//                 led1_r = 1'b1;
                 user_command_r <= NOP_CMD;
                 state <= WRITE_a;
               end
             end
    
           WRITE_a:
            begin
                user_address_r <= 25'b0;
                user_inputData_r <= 16'b10101;
                user_command_r <= WRITE_CMD;
                state <= WRITE_b;
            end
    
            WRITE_b:
             begin

                 if (sdram_user_cmd_ack == 1'b0) begin
                   user_address_r <= 25'b0;
                   user_command_r <= READ_CMD;
                   state <= READ_DATA;
                 end
             end
            

             READ_DATA:
              begin
                  //led1_r = 1'b1;
                  user_data_valid =sdram_user_data_valid;
                  if (user_data_valid == 1'b1) begin
                    led1_r = 1'b1;
                    user_data_1_r = sdram_user_output_data;
                    if (user_data_1_r == 16'b010) begin
                        led1_r = 1'b1;
                    end
                    else begin
                        led1_r = 1'b0;
                    end
                    //state <= READ_OK;
                  end
              end
                  
         endcase // case (state)
         //  
       end // always@ (negedge clk0)
endmodule