//Encoder TIM3 Init
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);

TIM_Time_user.TIM_Prescaler = 0;
TIM_Time_user.TIM_CounterMode = TIM_CounterMode_Up;
TIM_Time_user.TIM_Period = 256;
TIM_Time_user.TIM_ClockDivision = TIM_CKD_DIV1;

TIM_TimeBaseInit(TIM3, &TIM_Time_user);
TIM_EncoderInterfaceConfig(TIM3, TIM_EncoderMode_TI1, TIM_ICPolarity_Rising, TIM_ICPolarity_Rising);
TIM_Cmd(TIM3, ENABLE);
TIM3->CNT=0;
//Encoder TIM2 Init
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);

TIM_Time_user.TIM_Prescaler = 0;
TIM_Time_user.TIM_CounterMode = TIM_CounterMode_Up;
TIM_Time_user.TIM_Period = 256;
TIM_Time_user.TIM_ClockDivision = TIM_CKD_DIV1;

TIM_TimeBaseInit(TIM2, &TIM_Time_user);
TIM_EncoderInterfaceConfig(TIM2, TIM_EncoderMode_TI2, TIM_ICPolarity_Rising, TIM_ICPolarity_Rising);
TIM_Cmd(TIM2, ENABLE);
//TIM2->CCMR1 = TIM_CCMR1_CC2S_0 | TIM_CCMR1_CC1S_0;
TIM2->CCER |= TIM_CCER_CC1P;
TIM3->CCER |= TIM_CCER_CC1P;
TIM2->CNT=0;

void EXTI15_10_IRQHandler(void)
{
if(EXTI->PR & EXTI_PR_PR14) // прерывание канал А энкодера
{
EXTI->PR = EXTI_PR_PR14; // сбросить прерывание
if(GPIOB->IDR & ENC1) // определение направления импульса
{
if(GPIOB->IDR & ENC2)
{
ENCState = 0;
}
}
else
{
switch(ENCState)
{
case 0:
{
if(GPIOB->IDR & ENC2)
{
ENCState = 1;
}
break;
}
case 2:
{
key2buf(18);
ENCState = 0;
break;
}
}
}
}
if(EXTI->PR & EXTI_PR_PR15)
{
EXTI->PR = EXTI_PR_PR15; // сбросить прерывание
if(GPIOB->IDR & ENC2)
{
if(GPIOB->IDR & ENC1)
{
ENCState = 0;
}
}
else
{
switch(ENCState)
{
case 0:
{
if(GPIOB->IDR & ENC1)
{
ENCState = 2;
}
break;
}
case 1:
{
key2buf(17);
ENCState = 0;
break;
}
}

}
}
}

TIM3->PSC = 0; // TIM3CLK = PCLK/1
TIM3->ARR = 0xFFFF; // 16-bit resolution
TIM3->CNT = 0;
TIM3->CR1 = 0
| 0 * (TIM_CR1_CKD & -TIM_CR1_CKD) // Dead-time clock = timer clock
| 0 * TIM_CR1_ARPE // ARR not buffered
| 0 * (TIM_CR1_CMS & -TIM_CR1_CMS) // Unidirectional, not used
| 0 * TIM_CR1_DIR // Counting up, not used
| 0 * TIM_CR1_OPM // Counter not stopped at update event
| 0 * TIM_CR1_URS // Update request source, not used
| 1 * TIM_CR1_UDIS // Update event generation, 0 - enabled, 1 - disabled
| 1 * TIM_CR1_CEN // Counter enable
;

TIM3->SMCR = 0
| 0 * TIM_SMCR_ETP // External trigger polarity, not used
| 0 * TIM_SMCR_ECE // External clock mode 2 disabled
| 0 * (TIM_SMCR_ETPS & -TIM_SMCR_ETPS) // External trigger prescaler, not used
| 0 * (TIM_SMCR_ETF & -TIM_SMCR_ETF) // External trigger filter, not used
| 0 * TIM_SMCR_MSM // Master/slave mode, not used
| 0 * (TIM_SMCR_TS & -TIM_SMCR_TS) // Trigger selection, not used
| 3 * (TIM_SMCR_SMS & -TIM_SMCR_SMS) // Encoder mode, both edges
;

TIM3->CCMR1 = 0
// CC2 capture mode settings
| 1 * (TIM_CCMR1_IC2F & -TIM_CCMR1_IC2F) // IC2 Filter
| 0 * (TIM_CCMR1_IC2PSC & -TIM_CCMR1_IC2PSC) // IC2 Prescaler
| 1 * (TIM_CCMR1_CC2S & -TIM_CCMR1_CC2S) // Capture, TI1
// CC1 capture mode settings
| 1 * (TIM_CCMR1_IC1F & -TIM_CCMR1_IC1F) // IC1 Filter
| 0 * (TIM_CCMR1_IC1PSC & -TIM_CCMR1_IC1PSC) // IC1 Prescaler
| 1 * (TIM_CCMR1_CC1S & -TIM_CCMR1_CC1S) // Capture, TI1
;