Осваиваю FPGA, взял для внешнего FIFO Cyclone I. Для тактирования хочу взять частоту 100Мгц, как почти гарантированно работоспособную и в то же время минимизирующую задержки. Есть внешняя 25Мгц. MegaWizard "подарил" мне PLL с требуемой конфигурацией. Попытка запихать его в Modelsim-Altera потерпела неудачу. Делаю в Quartus: Start compilation, Start Analysis & Elaboration, Run EDA simulation tool - EDA Gate level simulation.
CODE
Warning: Parallel compilation is not licensed and has been disabled
Warning: Output port clk0 of PLL "alt_pll:LB0|altpll:altpll_component|pll" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
Warning: Parallel compilation is not licensed and has been disabled
Warning: Output port clk0 of PLL "alt_pll:LB0|altpll:altpll_component|pll" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
Warning: Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Warning: Parallel compilation is not licensed and has been disabled
Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled
Warning: Expected ENABLE_CLOCK_LATENCY to be set to ON but is set to OFF
Warning: Device family does not support board-level Boundary-Scan Description Language file generation
Warning: Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER
Warning: Output port clk0 of PLL "alt_pll:LB0|altpll:altpll_component|pll" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
Warning: Parallel compilation is not licensed and has been disabled
Warning: Output port clk0 of PLL "alt_pll:LB0|altpll:altpll_component|pll" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
Warning: Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Warning: Parallel compilation is not licensed and has been disabled
Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled
Warning: Expected ENABLE_CLOCK_LATENCY to be set to ON but is set to OFF
Warning: Device family does not support board-level Boundary-Scan Description Language file generation
Warning: Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER
Modelsim пытаться-то пытается, но как-то неубедительно:
Цитата
run -all
# ** Warning: Input clock freq. is not within VCO range : Cyclone PLL may not lock.
# Time: 60 ps Iteration: 7 Instance: /pll_sim/\LB0|altpll_component|pll\
# ** Warning: Input clock freq. is not within VCO range : Cyclone PLL may not lock.
# Time: 60 ps Iteration: 7 Instance: /pll_sim/\LB0|altpll_component|pll\
На втором периоде тактовой он уже знает, что частоту не захватить? по тексту ошибки полез результат посмотреть - так нет же, Nominal VCO frequency 800.0 MHz, в то же время в описании рабочий диапазон от 500 МГц до 1000 МГц).
Соответственно, выходной сигнал ровный, как пульс у покойника.
Подскажите новичку, куда копать?
Используется Quartus 11.0sp1 c Modelsim Altera Strtaer edition 6.6d
