void TM_MFRC522_Init(void)
   {
      
   TM_MFRC522_Reset();
   TM_MFRC522_WriteRegister(MFRC522_REG_T_MODE, 0x8D);
   TM_MFRC522_WriteRegister(MFRC522_REG_T_PRESCALER, 0x3E);
   TM_MFRC522_WriteRegister(MFRC522_REG_T_RELOAD_L, 30);          
   TM_MFRC522_WriteRegister(MFRC522_REG_T_RELOAD_H, 0);
   TM_MFRC522_WriteRegister(MFRC522_REG_TX_SELL, 0x15);
  
   TM_MFRC522_WriteRegister(MFRC522_REG_TX_AUTO, 0x40);
   TM_MFRC522_WriteRegister(MFRC522_REG_MODE, 0x3D);

      
    TM_MFRC522_AntennaOn();      //Open the antenna
      
   }

Рег. - Иниц. - Запрос+Стоп

0x01 - 0x20 - 0x0C
0x02 - 0x80 - 0xF7
0x03 - 0x00 - 0x00
0x04 - 0x14 - 0x44
0x05 - 0x00 - 0x04
0x06 - 0x00 - 0x00
0x07 - 0x29 - 0x39
0x08 - 0x00 - 0x05
0x09 - 0x26 - 0x00
0x0A - 0x00 - 0x00
0x0B - 0x08 - 0x08
0x0C - 0x10 - 0x10
0x0D - 0x00 - 0x04
0x0E - 0xA0 - 0xA0
0x0F - 0x00 <-
0x10 - 0x00 <-
0x11 - 0x3D <-
0x12 - 0x00 <-
0x13 - 0x00 <-
0x14 - 0x83 <-
0x15 - 0x40 <-
0x16 - 0x15 <-
0x17 - 0x84 <-
0x18 - 0x84 <-
0x19 - 0x4D <-
0x1A - 0x00 <-
0x1B - 0x00 <-
0x1C - 0x62 <-
0x1D - 0x00 <-
0x1E - 0x00 <-
0x1F - 0xEB <-

/**
* |----------------------------------------------------------------------
* | Copyright © Tilen Majerle, 2014
* |
* | This program is free software: you can redistribute it and/or modify
* | it under the terms of the GNU General Public License as published by
* | the Free Software Foundation, either version 3 of the License, or
* | any later version.
* |
* | This program is distributed in the hope that it will be useful,
* | but WITHOUT ANY WARRANTY; without even the implied warranty of
* | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* | GNU General Public License for more details.
* |
* | You should have received a copy of the GNU General Public License
* | along with this program. If not, see <http://www.gnu.org/licenses/>.
* |----------------------------------------------------------------------
*/

/**
* Status enumeration
*
* Used with most functions
*/

#include <stdio.h>

typedef enum
{
MI_OK = 0,
MI_NOTAGERR,
MI_ERR
} TM_MFRC522_Status_t;


#define MFRC522_CS_LOW MFRC522_CS_PORT->BSRRH = MFRC522_CS_PIN;
#define MFRC522_CS_HIGH MFRC522_CS_PORT->BSRRL = MFRC522_CS_PIN;

/* MFRC522 Commands */
#define PCD_IDLE 0x00 //NO action; Cancel the current command
#define PCD_AUTHENT 0x0E //Authentication Key
#define PCD_RECEIVE 0x08 //Receive Data
#define PCD_TRANSMIT 0x04 //Transmit data
#define PCD_TRANSCEIVE 0x0C //Transmit and receive data,
#define PCD_RESETPHASE 0x0F //Reset
#define PCD_CALCCRC 0x03 //CRC Calculate

/* Mifare_One card command word */
#define PICC_REQIDL 0x26 // find the antenna area does not enter hibernation
#define PICC_REQALL 0x52 // find all the cards antenna area
#define PICC_ANTICOLL 0x93 // anti-collision
#define PICC_SElECTTAG 0x93 // election card
#define PICC_AUTHENT1A 0x60 // authentication key A
#define PICC_AUTHENT1B 0x61 // authentication key B
#define PICC_READ 0x30 // Read Block
#define PICC_WRITE 0xA0 // write block
#define PICC_DECREMENT 0xC0 // debit
#define PICC_INCREMENT 0xC1 // recharge
#define PICC_RESTORE 0xC2 // transfer block data to the buffer
#define PICC_TRANSFER 0xB0 // save the data in the buffer
#define PICC_HALT 0x50 // Sleep

/* MFRC522 Registers */
//Page 0: Command and Status
#define MFRC522_REG_RESERVED00 0x00
#define MFRC522_REG_COMMAND 0x01
#define MFRC522_REG_COMM_IE_N 0x02
#define MFRC522_REG_DIV1_EN 0x03
#define MFRC522_REG_COMM_IRQ 0x04
#define MFRC522_REG_DIV_IRQ 0x05
#define MFRC522_REG_ERROR 0x06
#define MFRC522_REG_STATUS1 0x07
#define MFRC522_REG_STATUS2 0x08
#define MFRC522_REG_FIFO_DATA 0x09
#define MFRC522_REG_FIFO_LEVEL 0x0A
#define MFRC522_REG_WATER_LEVEL 0x0B
#define MFRC522_REG_CONTROL 0x0C
#define MFRC522_REG_BIT_FRAMING 0x0D
#define MFRC522_REG_COLL 0x0E
#define MFRC522_REG_RESERVED01 0x0F
//Page 1: Command
#define MFRC522_REG_RESERVED10 0x10
#define MFRC522_REG_MODE 0x11
#define MFRC522_REG_TX_MODE 0x12
#define MFRC522_REG_RX_MODE 0x13
#define MFRC522_REG_TX_CONTROL 0x14
#define MFRC522_REG_TX_AUTO 0x15
#define MFRC522_REG_TX_SELL 0x16
#define MFRC522_REG_RX_SELL 0x17
#define MFRC522_REG_RX_THRESHOLD 0x18
#define MFRC522_REG_DEMOD 0x19
#define MFRC522_REG_RESERVED11 0x1A
#define MFRC522_REG_RESERVED12 0x1B
#define MFRC522_REG_MIFARE 0x1C
#define MFRC522_REG_RESERVED13 0x1D
#define MFRC522_REG_RESERVED14 0x1E
#define MFRC522_REG_SERIALSPEED 0x1F
//Page 2: CFG
#define MFRC522_REG_RESERVED20 0x20
#define MFRC522_REG_CRC_RESULT_M 0x21
#define MFRC522_REG_CRC_RESULT_L 0x22
#define MFRC522_REG_RESERVED21 0x23
#define MFRC522_REG_MOD_WIDTH 0x24
#define MFRC522_REG_RESERVED22 0x25
#define MFRC522_REG_RF_CFG 0x26
#define MFRC522_REG_GS_N 0x27
#define MFRC522_REG_CWGS_PREG 0x28
#define MFRC522_REG__MODGS_PREG 0x29
#define MFRC522_REG_T_MODE 0x2A
#define MFRC522_REG_T_PRESCALER 0x2B
#define MFRC522_REG_T_RELOAD_H 0x2C
#define MFRC522_REG_T_RELOAD_L 0x2D
#define MFRC522_REG_T_COUNTER_VALUE_H 0x2E
#define MFRC522_REG_T_COUNTER_VALUE_L 0x2F
//Page 3:TestRegister
#define MFRC522_REG_RESERVED30 0x30
#define MFRC522_REG_TEST_SEL1 0x31
#define MFRC522_REG_TEST_SEL2 0x32
#define MFRC522_REG_TEST_PIN_EN 0x33
#define MFRC522_REG_TEST_PIN_VALUE 0x34
#define MFRC522_REG_TEST_BUS 0x35
#define MFRC522_REG_AUTO_TEST 0x36
#define MFRC522_REG_VERSION 0x37
#define MFRC522_REG_ANALOG_TEST 0x38
#define MFRC522_REG_TEST_ADC1 0x39
#define MFRC522_REG_TEST_ADC2 0x3A
#define MFRC522_REG_TEST_ADC0 0x3B
#define MFRC522_REG_RESERVED31 0x3C
#define MFRC522_REG_RESERVED32 0x3D
#define MFRC522_REG_RESERVED33 0x3E
#define MFRC522_REG_RESERVED34 0x3F
//Dummy byte
#define MFRC522_DUMMY 0x00

#define MFRC522_MAX_LEN 16


/**
* Private functions
*/
extern TM_MFRC522_Status_t TM_MFRC522_Check(uint8_t* id);


extern void TM_MFRC522_Test(void);
extern void TM_MFRC522_InitPins(void);
extern void TM_MFRC522_WriteRegister(uint8_t addr, uint8_t val);
extern uint8_t TM_MFRC522_ReadRegister(uint8_t addr);
extern TM_MFRC522_Status_t TM_MFRC522_ToCard(uint8_t command, uint8_t* sendData, uint8_t sendLen, uint8_t* backData, uint16_t* backLen);
extern TM_MFRC522_Status_t TM_MFRC522_Request(uint8_t reqMode, uint8_t* TagType);
extern TM_MFRC522_Status_t TM_MFRC522_Anticoll(uint8_t* serNum);
extern void TM_MFRC522_SetBitMask(uint8_t reg, uint8_t mask);
extern void TM_MFRC522_ClearBitMask(uint8_t reg, uint8_t mask);
extern void TM_MFRC522_AntennaOn(void);
extern void TM_MFRC522_AntennaOff(void);
extern void TM_MFRC522_Reset(void);
extern void TM_MFRC522_Halt(void);
extern void TM_MFRC522_CalculateCRC(uint8_t* pIndata, uint8_t len, uint8_t* pOutData);
void *memcpy(void *dst, const void *src, size_t len);

uint8_t OTVRC522[2];
uint8_t BUFRC522[48];
uint8_t BUFWR522[48];
uint8_t ZAPRC522[2];


Сама функция:

TM_MFRC522_Status_t TM_MFRC522_Check(uint8_t* id)
{
TM_MFRC522_Status_t status;
//Find cards, return card type
status = TM_MFRC522_Request(PICC_REQIDL, id);
if (status == MI_OK)
{
//Card detected
//Anti-collision, return card serial number 4 bytes
status = TM_MFRC522_Anticoll(id);

}


//TM_MFRC522_Halt(); //Command card into hibernation

HAL_Delay(20);


return status;
}


Запрос:

TM_MFRC522_Status_t TM_MFRC522_Request(uint8_t reqMode, uint8_t* TagType)
{
TM_MFRC522_Status_t status;
uint16_t backBits; //The received data bits

TM_MFRC522_WriteRegister(MFRC522_REG_BIT_FRAMING, 0x07); //TxLastBists = BitFramingReg[2..0] ???

TagType[0] = reqMode;
HAL_GPIO_WritePin(GPIOE, GPIO_PIN_8, GPIO_PIN_RESET);

status = TM_MFRC522_ToCard(PCD_TRANSCEIVE, TagType, 1, TagType, &backBits);

if ((status != MI_OK) || (backBits != 0x10))
{
status = MI_ERR;
}

return status;
}

Ну и самая тяжелая часть:

TM_MFRC522_Status_t TM_MFRC522_ToCard(uint8_t command, uint8_t* sendData, uint8_t sendLen, uint8_t* backData, uint16_t* backLen)
{
TM_MFRC522_Status_t status = MI_ERR;
uint8_t irqEn = 0x00;
uint8_t waitIRq = 0x00;
uint8_t lastBits;
uint8_t n;
uint16_t i;

switch (command)
{
case PCD_AUTHENT:
{
irqEn = 0x12;
waitIRq = 0x10;
break;
}
case PCD_TRANSCEIVE:
{
irqEn = 0x77;
waitIRq = 0x30;
break;
}
default:
break;
}


TM_MFRC522_WriteRegister(MFRC522_REG_COMM_IE_N, irqEn | 0x80);
TM_MFRC522_ClearBitMask(MFRC522_REG_COMM_IRQ, 0x80);
TM_MFRC522_SetBitMask(MFRC522_REG_FIFO_LEVEL, 0x80);

TM_MFRC522_WriteRegister(MFRC522_REG_COMMAND, PCD_IDLE);

//Writing data to the FIFO
for (i = 0; i < sendLen; i++)
{
TM_MFRC522_WriteRegister(MFRC522_REG_FIFO_DATA, sendData[i]);
}

//Execute the command
TM_MFRC522_WriteRegister(MFRC522_REG_COMMAND, command);
if (command == PCD_TRANSCEIVE)
{
TM_MFRC522_SetBitMask(MFRC522_REG_BIT_FRAMING, 0x80); //StartSend=1,transmission of data starts
}

//Waiting to receive data to complete
i = 2000; //i according to the clock frequency adjustment, the operator M1 card maximum waiting time 25ms???
do
{
//CommIrqReg[7..0]
//Set1 TxIRq RxIRq IdleIRq HiAlerIRq LoAlertIRq ErrIRq TimerIRq
n = TM_MFRC522_ReadRegister(MFRC522_REG_COMM_IRQ);
i--;
}
while ((i!=0) && !(n&0x01) && !(n&waitIRq));

TM_MFRC522_ClearBitMask(MFRC522_REG_BIT_FRAMING, 0x80); //StartSend=0
HAL_GPIO_WritePin(GPIOE, GPIO_PIN_8, GPIO_PIN_SET);

if (i != 0)
{
if (!(TM_MFRC522_ReadRegister(MFRC522_REG_ERROR) & 0x1B))
{
status = MI_OK;
if (n & irqEn & 0x01)
{
status = MI_NOTAGERR;
}

if (command == PCD_TRANSCEIVE)
{
n = TM_MFRC522_ReadRegister(MFRC522_REG_FIFO_LEVEL);

lastBits = TM_MFRC522_ReadRegister(MFRC522_REG_CONTROL) & 0x07;
VREMUART[0]=TM_MFRC522_ReadRegister(MFRC522_REG_COMMAND);
if (lastBits)
{
*backLen = (n - 1) * 8 + lastBits;
}
else
{
*backLen = n * 8;
}

if (n == 0)
{
n = 1;
}
if (n > MFRC522_MAX_LEN)
{
n = MFRC522_MAX_LEN;
}

//Reading the received data in FIFO
for (i = 0; i < n; i++)
{
backData[i] = TM_MFRC522_ReadRegister(MFRC522_REG_FIFO_DATA);
}
}
}
else
{
status = MI_ERR;
}
}

return status;
}

{
case PCD_AUTHENT:
{
irqEn = 0x12;
waitIRq = 0x10;
break;
}
case PCD_TRANSCEIVE:
{
irqEn = 0x77;
waitIRq = 0x30;
break;
}
default:
break;
}

TM_MFRC522_ReadRegister(MFRC522_REG_BIT_FRAMING);

TM_MFRC522_WriteRegister(MFRC522_REG_COMM_IE_N, irqEn | 0x80);
TM_MFRC522_ClearBitMask(MFRC522_REG_COMM_IRQ, 0x80);
TM_MFRC522_SetBitMask(MFRC522_REG_FIFO_LEVEL, 0x80);
TM_MFRC522_ReadRegister(MFRC522_REG_BIT_FRAMING);

    TM_MFRC522_WriteRegister(MFRC522_REG_COMM_IE_N, irqEn | 0x80);
    TM_MFRC522_ClearBitMask(MFRC522_REG_COMM_IRQ, 0x80);
    TM_MFRC522_SetBitMask(MFRC522_REG_FIFO_LEVEL, 0x80);
        TM_MFRC522_ReadRegister(MFRC522_REG_BIT_FRAMING);