DelayLine: process (iclk,iReset)
begin
    if (iReset = '1') then
                address_rd <= (others => '0');
        wren <= '0';
    elsif (RISING_EDGE(iclk)) then
        wren <= '1';
        address_rd <= address_rd+1;
        address_wr <= address_rd + idata_delay;
        data_wr1 <= idata_sdr_a(11 downto 0);
        data_wr2 <= idata_sdr_a(23 downto 12);
        data_wr3 <= idata_sdr_b(11 downto 0);
        data_wr4 <= idata_sdr_b(23 downto 12);
        odata_sdr_a(11 downto 0) <= data_rd1;
        odata_sdr_a(23 downto 12) <= data_rd2;
        odata_sdr_b(11 downto 0) <= data_rd3;
        odata_sdr_b(23 downto 12) <= data_rd4;
    end if;
end process;