помогите разобраться почему описаная схема по управлению лцд-дисплеем отказывается работать в железе...
Компелятор не ругаеться, в симуляторе тоже все хорошо выглядит. Я с начала думал что паузы между командами слишком маленькие, увеличил, всеравно не работает, но не так чтобы совсем не работает, не пишит текст. Инициализацию принемает, а текст не пишит
ну и сам Код:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lcd_v5 is port
(
clk : in std_logic; -- System clk
-- daten_bereit : in std_logic;
-- data_input : in std_logic_vector(7 downto 0);
busy : out std_logic := '1'; -- busy Flag
rs : out std_logic := '0'; -- data or instruction, instruction = '0', data = '1'
rw : out std_logic := '0'; -- read or write, read = '1', write = '0'
enable_lcd : out std_logic := '0'; -- enable for read of write
data : out std_logic_vector(7 downto 0) := (others => '0') -- daten
);
end entity;
architecture beh of lcd_v5 is
type zustaende is (begining, waitx, ini_data_send, lcd_enable, lcd_desable, ini_loop, ready);
signal zustand : zustaende := begining;
type mem_data is array(0 to 11) of std_logic_vector(7 downto 0);
constant daten : mem_data :=
(
x"30", -- data_reset(0) "0011 0000"
x"30", -- data_reset(1) "0011 0000"
x"30", -- data_reset(2) "0011 0000"
x"3c", -- data_ini_1(3) "0011 1100"
x"0f", -- data_ini_2(4) "0000 1111"
x"07", -- data_ini_3(5) "0000 0111"
x"01", -- data_ini_4(6) "0000 0001"
x"59", -- Y(7)
x"65", -- e(8)
x"61", -- a(9)
x"21", -- !(10)
x"00" -- (11)
);
type delay_type is array(0 to 6) of std_logic_vector(23 downto 0);
constant delay : delay_type :=
(
x"4c4b40", -- 100 ms(0)
x"033450", -- 4.2ms(1)
x"0013ba", -- 101us(2)
x"0009c4", -- delay_50us(3)
x"000032", -- delay_1us(4)
x"2625a0", -- delay_50ms(5)
x"030d40" -- delay_4ms(6)
);
signal addr_delay : integer range 0 to 6 := 0;
signal addr_delay_i : integer range 0 to 6 := 0;
signal addr_data : integer range 0 to 11 := 0;
signal counter : std_logic_vector(23 downto 0) := (others => '0');
signal cnt_en : std_logic := '0';
signal cnt_fert : boolean := false;
signal initialisierung : boolean := false;
signal pause_halten : boolean := true;
signal daten_gesendet : std_logic_vector(1 downto 0) := "00";
signal versions_nr : boolean := false;
signal load : std_logic := '0';
signal data_out : std_logic_vector(7 downto 0) := (others => '0');
begin
process(clk)
variable cnt_intern : integer range -2 to 5000000 := 2;
begin
if rising_edge(clk) then
if cnt_en = '1' then
if load = '1' then
cnt_intern := to_integer(unsigned(counter));
else
cnt_intern := cnt_intern - 1;
cnt_fert <= false;
end if;
if cnt_intern = 0 then
cnt_fert <= true;
end if;
end if;
end if;
end process;
-- automat --
process(clk)
variable durchlauf : integer range 0 to 12 := 0;
begin
if (rising_edge(clk)) then
case zustand is
when begining => counter <= delay(addr_delay);
cnt_en <= '1';
load <= '1';
rw <= '0';
busy <= '1';
zustand <= waitx;
if versions_nr = true then
rs <= '1';
else
rs <= '0';
end if;
when waitx => load <= '0';
if cnt_fert = true then
if initialisierung = false then
case daten_gesendet is
when "01" => zustand <= lcd_enable;
cnt_en <= '0';
when "10" => cnt_en <= '0';
zustand <= lcd_desable;
when others => data_out <= (others => '0');
if pause_halten = true then
enable_lcd <= '0';
cnt_en <= '0';
pause_halten <= false;
zustand <= ini_data_send;
else
cnt_en <= '0';
enable_lcd <= '0';
addr_delay <= addr_delay_i;
zustand <= ini_loop;
durchlauf := durchlauf + 1;
end if;
end case;
else
cnt_en <= '0';
zustand <= ready;
durchlauf := 0;
end if;
else
zustand <= waitx;
end if;
when ini_data_send => data_out <= daten(addr_data);
addr_delay <= 4;
daten_gesendet <= "01";
zustand <= begining;
when lcd_enable => addr_delay <= 4;
enable_lcd <= '1';
zustand <= begining;
daten_gesendet <= "10";
when lcd_desable => enable_lcd <= '0';
zustand <= begining;
daten_gesendet <= "00";
when ini_loop => data_out <= (others => '0');
if durchlauf > 2 then
addr_data <= addr_data + 1;
addr_delay_i <= 3;
addr_delay <= 3;
pause_halten <= true;
zustand <= begining;
if durchlauf = 7 then
versions_nr <= true;
addr_data <= addr_data + 1;
addr_delay <= 5;
addr_delay_i <= 5;
pause_halten <= true;
zustand <= begining;
end if;
else
addr_delay <= addr_delay + 1;
addr_delay_i <= addr_delay_i + 1;
addr_data <= addr_data + 1;
pause_halten <= true;
zustand <= begining;
end if;
if durchlauf >= 11 then
durchlauf := 0;
addr_data <= addr_data + 1;
addr_delay <= 6;
initialisierung <= true;
zustand <= begining;
end if;
when ready => zustand <= ready;
end case;
end if;
end process;
data <= data_out;
end beh;
