Код: if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK)
  {
    Error_Handler();
  }

///Install SDRAM stm32f439
FMC_Bank5_6 -> SDCR[0] = FMC_SDCR1_NC_9bits
|FMC_SDCR1_NR_13bits
|FMC_SDCR1_MWID_16bits
|FMC_SDCR1_NB_4banks
|FMC_SDCR1_CAS_2cycle
//|FMC_SDCR1_SDCLK_3x
|FMC_SDCR1_SDCLK_2x
|FMC_SDCR2_RBURST
|FMC_SDCR1_WP
|FMC_SDCR1_RPIPE_1delay; //FMC_SDCR1_RPIPE_1delay FMC_SDCR1_RPIPE_3delay

FMC_Bank5_6->SDTR[0] = (0x00000001) /// TMRD время между записью в MODE-REGISTER и ACTIVATE/1 /2
|(0x00000005 << 4) /// TXSR время между SELF-REFRESHING и ACTIVATE (exit self-refresh mode)/5 /7
|(0x00000002 << 8) /// TRAS минимальное время между SELF-REFRESH/2 /4
|(0x00000006 << 12) /// TRC время между двумя командами REFRESH/5 /7
|(0x00000003 << 16) /// TWR задержка между командой WRITE и вызовом PRECHARGE/1 /2
|(0x00000001 << 20) /// TRP время между командой PRECHARGE и любой другой командой/1 /1
|(0x00000002 << 24); /// TRCD время между подачей команды ACTIVATE и появлением данных на шинеС/1 /2
///TWR >= TRAS - TRCD and TWR >= TRC - TRCD - TRP
FMC_Bank5_6->SDCMR = FMC_SDCMR_CTB1 | FMC_SDCMR_MODE_Config_Enable;
tmp = FMC_Bank5_6->SDSR & 0x00000020;
timeout = 0xFFFF;
while((tmp != 0) && (timeout-- > 0))
{
tmp = FMC_Bank5_6->SDSR & 0x00000020;
}

delay(10000);
/// PALL command
FMC_Bank5_6->SDCMR = FMC_SDCMR_CTB1 | FMC_SDCMR_MODE_PALL;
timeout = 0xFFFF; tmp = 10;
while((tmp != 0) && (timeout-- > 0))
{
tmp = FMC_Bank5_6->SDSR & 0x00000020;
}
/// Auto refresh command
FMC_Bank5_6->SDCMR = (0x00000003 << 5) | FMC_SDCMR_CTB1 | FMC_SDCMR_MODE_Self_refresh;
/// Количество рефлеш минимум 2
timeout = 0xFFFF; tmp = 10;
while((tmp != 0) && (timeout-- > 0))
{
tmp = FMC_Bank5_6->SDSR & 0x00000020;
}
// MRD register program
tmp = (((((HSE_gz / (((RCC->PLLCFGR)<<26)>>26))*(((RCC->PLLCFGR)<<17)>>23))/(((((RCC->PLLCFGR)<<14)>>30)<<1)+2))/2000)*64)/8192;
FMC_Bank5_6->SDCMR = (tmp << 9) | FMC_SDCMR_CTB1 | FMC_SDCMR_MODE_Load_Mode;
/// 64mc/(размер блока Row Addresses(8192)) * (тактовая частота чипа)
timeout = 0xFFFF; tmp = 10;
while((tmp != 0) && (timeout-- > 0))
{
tmp = FMC_Bank5_6->SDSR & 0x00000020;
}
tmp = (((((((HSE_gz / (((RCC->PLLCFGR)<<26)>>26))*(((RCC->PLLCFGR)<<17)>>23))/(((((RCC->PLLCFGR)<<14)>>30)<<1)+2))/2000)*64)/8192)<<1) | FMC_Bank5_6->SDRTR;
FMC_Bank5_6->SDRTR = (tmp | (0x000002C5<<1)) | 1<<14; // время регена + вкл регена
/// Refresh rate = (COUNT) * SDRAM clock frequency
/// SDRAM refresh period = 64 mc
/// COUNT = (SDRAM refresh period / Number of rows )
/// Refresh rate = 0.064 / (8192rows + 4) ) * 84000000 , ~ 656 ( 0x290 )

FMC_Bank5_6->SDCR[0] &= (~FMC_SDCR1_WP);// снятие защиты от записи
// timeout =0;
for(tmp = 0xc0000000; tmp < 0xC1FFFFFC; tmp += 4) ///32Mb 0.873 ms
{
*((volatile uint32_t *)tmp) = 0x00000000;// timeout;
}

MEMORY
{
ROM (rx) : ORIGIN = 0x08000000, LENGTH = 2048K
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 192K
SRAM (rwx) : ORIGIN = 0xD0000000, LENGTH = 64K
CCRAM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
SDRAM (rwx) : ORIGIN = 0xC0000000, LENGTH = 16384K
BKRAM (rw) : ORIGIN = 0x40024000, LENGTH = 4K
}

--------------
/* размещение констант в SDRAM */
_sicsdram = LOADADDR(.csdram);
.csdram :
{
. = ALIGN(4);
_scsdram = .; /* глобальный символ начала SDRAM */
*(.csdram)
*(.csdram*)
. = ALIGN(4);
_ecsdram = .; /* глобальный символ конца SDRAM */
} > SDRAM AT> FLASH

---------------
*.s файл

bl SystemInit

ldr r0, =_scsdram
ldr r1, =_sicsdram
ldr r2, =_ecsdram
LoopCopySdram:
cmp r0, r2
ittt ne
ldrne r3, [r1], #4
strne r3, [r0], #4
bne LoopCopySdram

bl main

---------

макрос
#define SDram __attribute__((section(".csdram")))
----------
глобальные переменные
SDram const uint16_t Font[размер] ={дата};

/* Wait until the SDRAM controller is ready */
  while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
  {
  }
  /* Send the  first command */
  FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
  
  /* Wait until the SDRAM controller is ready */
  while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
  {
  }
  /* Send the second command */
  FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);