PARAMETER VERSION = 2.1.0


PORT CLK_IN = net_CLK_IN, DIR = I, SIGIS = CLK
PORT axi_emc_0_Mem_A_pin = axi_emc_0_Mem_A, DIR = O, VEC = [31:0]
PORT axi_emc_0_Mem_CEN_pin = axi_emc_0_Mem_CEN, DIR = O
PORT axi_emc_0_Mem_OEN_pin = axi_emc_0_Mem_OEN, DIR = O
PORT axi_emc_0_Mem_WEN_pin = axi_emc_0_Mem_WEN, DIR = O
PORT axi_emc_0_Mem_ADV_LDN_pin = axi_emc_0_Mem_ADV_LDN, DIR = O
PORT axi_emc_0_Mem_DQ_pin = axi_emc_0_Mem_DQ, DIR = IO, VEC = [31:0]
PORT axi_gpio_0_GPIO_IO_pin = axi_gpio_0_GPIO_IO, DIR = IO, VEC = [31:0]


BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER HW_VER = 4.03.a
PARAMETER C_CLKIN_FREQ = 100000000
PARAMETER C_CLKOUT0_FREQ = 100000000
PARAMETER C_CLKOUT0_GROUP = PLL0
PORT LOCKED = clock_generator_0_LOCKED_0
PORT CLKOUT0 = clock_generator_0_CLKOUT0
PORT RST = net_gnd
PORT CLKIN = net_CLK_IN
END

BEGIN proc_sys_reset
PARAMETER INSTANCE = reset_0
PARAMETER HW_VER = 3.00.a
PORT Dcm_locked = clock_generator_0_LOCKED_0
PORT MB_Debug_Sys_Rst = debug_module_0_Debug_SYS_Rst
PORT Ext_Reset_In = net_gnd
PORT Slowest_sync_clk = clock_generator_0_CLKOUT0
PORT MB_Reset = reset_0_MB_Reset
PORT Bus_Struct_Reset = reset_0_Bus_Struct_Reset
END

BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 8.50.c
PARAMETER C_USE_BARREL = 1
PARAMETER C_USE_ICACHE = 0
PARAMETER C_USE_DCACHE = 0
PARAMETER C_INTERCONNECT = 2
PARAMETER C_DEBUG_ENABLED = 1
BUS_INTERFACE DEBUG = debug_module_0_MBDEBUG_0
BUS_INTERFACE M_AXI_DP = axi_interconnect_0
BUS_INTERFACE M_AXI_IP = axi_interconnect_0
BUS_INTERFACE INTERRUPT = axi_intc_0_INTERRUPT
BUS_INTERFACE DLMB = lmb_v10_0
BUS_INTERFACE ILMB = lmb_v10_1
PORT MB_RESET = reset_0_MB_Reset
END

BEGIN mdm
PARAMETER INSTANCE = debug_module_0
PARAMETER HW_VER = 2.10.a
PARAMETER C_INTERCONNECT = 2
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = microblaze_0.M_AXI_DP
PARAMETER C_BASEADDR = 0x04002000
PARAMETER C_HIGHADDR = 0x04002FFF
BUS_INTERFACE MBDEBUG_0 = debug_module_0_MBDEBUG_0
BUS_INTERFACE S_AXI = axi_interconnect_0
PORT Debug_SYS_Rst = debug_module_0_Debug_SYS_Rst
PORT S_AXI_ACLK = clock_generator_0_CLKOUT0
PORT Interrupt = debug_module_0_Interrupt
END

BEGIN axi_interconnect
PARAMETER INSTANCE = axi_interconnect_0
PARAMETER HW_VER = 1.06.a
PORT INTERCONNECT_ACLK = clock_generator_0_CLKOUT0
PORT INTERCONNECT_ARESETN = reset_0_Bus_Struct_Reset
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = bram_cntlr_0
PARAMETER HW_VER = 3.10.c
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x0000ffff
BUS_INTERFACE SLMB = lmb_v10_1
BUS_INTERFACE BRAM_PORT = bram_cntlr_0_BRAM_PORT
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = bram_cntlr_1
PARAMETER HW_VER = 3.10.c
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x0000ffff
BUS_INTERFACE SLMB = lmb_v10_0
BUS_INTERFACE BRAM_PORT = bram_cntlr_1_BRAM_PORT
END

BEGIN lmb_v10
PARAMETER INSTANCE = lmb_v10_0
PARAMETER HW_VER = 2.00.b
PORT LMB_Clk = clock_generator_0_CLKOUT0
PORT SYS_Rst = reset_0_MB_Reset
END

BEGIN lmb_v10
PARAMETER INSTANCE = lmb_v10_1
PARAMETER HW_VER = 2.00.b
PORT LMB_Clk = clock_generator_0_CLKOUT0
PORT SYS_Rst = reset_0_MB_Reset
END

BEGIN bram_block
PARAMETER INSTANCE = bram_block_0
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = bram_cntlr_0_BRAM_PORT
BUS_INTERFACE PORTB = bram_cntlr_1_BRAM_PORT
END

BEGIN axi_intc
PARAMETER INSTANCE = axi_intc_0
PARAMETER HW_VER = 1.04.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = microblaze_0.M_AXI_DP
PARAMETER C_BASEADDR = 0x04003000
PARAMETER C_HIGHADDR = 0x04003FFF
BUS_INTERFACE S_AXI = axi_interconnect_0
BUS_INTERFACE INTERRUPT = axi_intc_0_INTERRUPT
PORT S_AXI_ACLK = clock_generator_0_CLKOUT0
PORT Intr = debug_module_0_Interrupt & axi_timer_0_Interrupt
END

BEGIN axi_emc
PARAMETER INSTANCE = axi_emc_0
PARAMETER HW_VER = 1.03.b
PARAMETER C_INTERCONNECT_S_AXI_MEM_MASTERS = microblaze_0.M_AXI_DP
PARAMETER C_S_AXI_MEM_PROTOCOL = axi4lite
PARAMETER C_S_AXI_MEM_ID_WIDTH = 1
PARAMETER C_MAX_MEM_WIDTH = 32
PARAMETER C_S_AXI_MEM0_BASEADDR = 0x05000000
PARAMETER C_S_AXI_MEM0_HIGHADDR = 0x057FFFFF
BUS_INTERFACE S_AXI_MEM = axi_interconnect_0
PORT RdClk = clock_generator_0_CLKOUT0
PORT S_AXI_ACLK = clock_generator_0_CLKOUT0
PORT Mem_A = axi_emc_0_Mem_A
PORT Mem_CEN = axi_emc_0_Mem_CEN
PORT Mem_OEN = axi_emc_0_Mem_OEN
PORT Mem_WEN = axi_emc_0_Mem_WEN
PORT Mem_ADV_LDN = axi_emc_0_Mem_ADV_LDN
PORT Mem_DQ = axi_emc_0_Mem_DQ
END

BEGIN axi_gpio
PARAMETER INSTANCE = axi_gpio_0
PARAMETER HW_VER = 1.01.b
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = microblaze_0.M_AXI_DP
PARAMETER C_BASEADDR = 0x04000000
PARAMETER C_HIGHADDR = 0x04000FFF
BUS_INTERFACE S_AXI = axi_interconnect_0
PORT S_AXI_ACLK = clock_generator_0_CLKOUT0
PORT GPIO_IO = axi_gpio_0_GPIO_IO
END

BEGIN axi_timer
PARAMETER INSTANCE = axi_timer_0
PARAMETER HW_VER = 1.03.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = microblaze_0.M_AXI_DP
PARAMETER C_BASEADDR = 0x04001000
PARAMETER C_HIGHADDR = 0x04001FFF
BUS_INTERFACE S_AXI = axi_interconnect_0
PORT S_AXI_ACLK = clock_generator_0_CLKOUT0
PORT Interrupt = axi_timer_0_Interrupt
END

#include <stdio.h>
#include "xparameters.h"
#include "xil_cache.h"
#include "xintc.h"
#include "xintc_l.h"
#include "intc_header.h"
#include "xbasic_types.h"
#include "xgpio.h"
#include "xgpio_l.h"
#include "gpio_header.h"
#include "xtmrctr.h"
#include "xtmrctr_l.h"
#include "tmrctr_header.h"
#include "tmrctr_intr_header.h"
#include <xuartlite.h>
#include <xuartlite_l.h>

// Global variables: count is the count displayed using the
// LEDs, and timer_count is the interrupt frequency.

    unsigned int count = 1; // default count
    unsigned int timer_count = 1; // default timer_count
    XGpio pin;
    // uartlite interrupt service routine

    void uart_int_handler(void *baseaddr_p)
    {
        char c;
        // till uart FIFOs are empty
        while (!XUartLite_IsReceiveEmpty(XPAR_DEBUG_MODULE_0_BASEADDR))
        {
            // read a character
            c = XUartLite_RecvByte(XPAR_DEBUG_MODULE_0_BASEADDR);
            // if the character is between "0" and "9"
                if ((c>47) && (c<58))
                    {
                        timer_count = c-48;
                        // print character on hyperterminal (STDOUT)
                        putnum(timer_count);
                        // Set timer with new value of timer_count
                        XTmrCtr_SetLoadReg(XPAR_AXI_TIMER_0_BASEADDR, 0, (timer_count*timer_count+1) * 1000);
                    }
        }
    }

    // timer interrupt service routine
    void timer_int_handler(void * baseaddr_p)
    {
        unsigned int csr;
        unsigned int gpio_data;
        // Read timer 0 CSR to see if it raised the interrupt
        csr = XTmrCtr_GetControlStatusReg(XPAR_AXI_TIMER_0_BASEADDR, 0);
            if (csr & XTC_CSR_INT_OCCURED_MASK)
            {
                // Increment the count
                if ((count <<= 1) > 8)
                {
                    count = 1;
                }
        // Write value to gpio. 0 means light up, hence count is negated
        gpio_data = ~count;
        XGpio_WriteReg(XPAR_AXI_GPIO_0_BASEADDR,0, gpio_data);
        // Clear the timer interrupt

        XTmrCtr_SetControlStatusReg(XPAR_AXI_TIMER_0_BASEADDR, 0, csr);
            }
    }

int main()
{

   Xil_ICacheEnable();
   Xil_DCacheEnable();

  // print("---Entering main---\n\r");

      // Enable microblaze interrupts
      microblaze_enable_interrupts();
      // Connect uart interrupt handler that will be called when an interrupt for the uart occurs

      XIntc_RegisterHandler(XPAR_AXI_INTC_0_BASEADDR, XPAR_AXI_INTC_0_DEBUG_MODULE_0_INTERRUPT_INTR , (XInterruptHandler)uart_int_handler, (void *)XPAR_DEBUG_MODULE_0_BASEADDR);
      // Start the interrupt controller
      XIntc_MasterEnable(XPAR_INTC_SINGLE_BASEADDR);
      // Set the gpio as output on high 3 bits (LEDs)
      XGpio_SetDataDirection(&pin,1, 0x00);
      // set the number of cycles the timer counts before interrupting
      XTmrCtr_SetLoadReg(XPAR_AXI_TIMER_0_BASEADDR, 0, (timer_count*timer_count+1) * 1000);
      // reset the timers, and clear interrupts
      XTmrCtr_SetControlStatusReg(XPAR_AXI_TIMER_0_BASEADDR, 0, XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK );
      // Enable timer and uart interrupts in the interrupt controller
      XIntc_EnableIntr(XPAR_AXI_INTC_0_BASEADDR, XPAR_AXI_TIMER_0_INTERRUPT_MASK| XPAR_DEBUG_MODULE_0_INTERRUPT_MASK);
      // Enable Uartlite interrupt
      XUartLite_EnableIntr(XPAR_DEBUG_MODULE_0_BASEADDR);
      // start the timers
      XTmrCtr_SetControlStatusReg(XPAR_AXI_TIMER_0_BASEADDR, 0,XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK);
      // Wait for interrupts to occur
      while (1)
          {
              XGpio_DiscreteWrite(&pin,1,0);
          };

   print("---Exiting main---\n\r");

   Xil_DCacheDisable();
   Xil_ICacheDisable();

   return 0;
}