USE std.textio.all;

...

file hopp_sync_f: text open read_mode is "d:\zynq-sdk\shared\vivado\ip_repo\modem_fhss_2.0\src\modemFHSS\others\sim_data\hopp\ideal\hopp_sync.dat";
file hopp_re_f: text open read_mode is "d:\zynq-sdk\shared\vivado\ip_repo\modem_fhss_2.0\src\modemFHSS\others\sim_data\hopp\ideal\hopp_re.dat";
file hopp_im_f: text open read_mode is "d:\zynq-sdk\shared\vivado\ip_repo\modem_fhss_2.0\src\modemFHSS\others\sim_data\hopp\ideal\hopp_im.dat";
file hopp_freq_f: text open read_mode is "d:\zynq-sdk\shared\vivado\ip_repo\modem_fhss_2.0\src\modemFHSS\others\sim_data\hopp\ideal\hopp_freq.dat";

...

                when ADDR_FHSS_HOPP_C =>
                    if (not endfile(hopp_sync_f)) then
                        readline(hopp_sync_f, sync_l);
                        readline(hopp_re_f, re_l);
                        readline(hopp_im_f, im_l);
                        readline(hopp_freq_f, oth_l);
                        
                        read(sync_l, sync_i);
                        read(re_l, re_i);
                        read(im_l, im_i);
                        read(oth_l, oth_i);
                        
                        buf_sync(0 downto 0) := std_logic_vector(to_unsigned(sync_i,1));
                        buf_re := std_logic_vector(to_signed(re_i,16));
                        buf_im := std_logic_vector(to_signed(im_i,16));
                        buf_oth := std_logic_vector(to_unsigned(oth_i,32));
                        
                        sync_o <= buf_sync(0);
                        data_re_o <= buf_re(data_w_g-1 downto 0);
                        data_im_o <= buf_im(data_w_g-1 downto 0);
                        oth_o <= buf_oth(oth_w_g-1 downto 0);
                    else
                        sync_o <= '0';
                        valid_o <= '0';
                        data_re_o <= (others => '0');
                        data_im_o <= (others => '0');
                        oth_o <= (others => '0');
                    end if;

ip_repo\[name_core]\[name_core]_v0_project\[name_core_v0_project.sim\sim_1\behav\

file tx_sync_f: text open read_mode is "../../tx_ideal_sync.dat";
file tx_re_f: text open read_mode is "../../tx_ideal_re.dat";
file tx_im_f: text open read_mode is "../../tx_ideal_im.dat";