Вроде бы всё делаю как надо:
Код
create_clock -name ADC_DCO_P -period 4.166 [get_ports ADC_DCO_P]
set_input_delay -clock ADC_DCO_P -rise -max 1.880 [get_ports {ADC_OUT*}]
set_input_delay -clock ADC_DCO_P -rise -min 0.200 [get_ports {ADC_OUT*}]
set_input_delay -clock ADC_DCO_P -clock_fall -max -add_delay 1.880 [get_ports {ADC_OUT*}]
set_input_delay -clock ADC_DCO_P -clock_fall -min -add_delay 0.200 [get_ports {ADC_OUT*}]
set_false_path -rise_from [get_clocks ADC_DCO_P] -through [get_pins .*IDDR.*D -regexp -hierarchical] -fall_to [get_clocks ADC_DCO_P]
set_false_path -fall_from [get_clocks ADC_DCO_P] -through [get_pins .*IDDR.*D -regexp -hierarchical] -rise_to [get_clocks ADC_DCO_P]
set_input_delay -clock ADC_DCO_P -rise -max 1.880 [get_ports {ADC_OUT*}]
set_input_delay -clock ADC_DCO_P -rise -min 0.200 [get_ports {ADC_OUT*}]
set_input_delay -clock ADC_DCO_P -clock_fall -max -add_delay 1.880 [get_ports {ADC_OUT*}]
set_input_delay -clock ADC_DCO_P -clock_fall -min -add_delay 0.200 [get_ports {ADC_OUT*}]
set_false_path -rise_from [get_clocks ADC_DCO_P] -through [get_pins .*IDDR.*D -regexp -hierarchical] -fall_to [get_clocks ADC_DCO_P]
set_false_path -fall_from [get_clocks ADC_DCO_P] -through [get_pins .*IDDR.*D -regexp -hierarchical] -rise_to [get_clocks ADC_DCO_P]
LVDS данные со входа поступают на IBUFDS
Код
IBUFDS #(
.DIFF_TERM("TRUE"), // Differential Termination
.IBUF_LOW_PWR("FALSE"), // Low power="TRUE", Highest performance="FALSE"
.IOSTANDARD("LVDS") // Specify the input I/O standard
) IBUFDS_adc_A (
.O (adc_A_pre), // Buffer output
.I (ADC_OUT_1A_P), // Diff_p buffer input (connect directly to top-level port)
.IB (ADC_OUT_1A_N) // Diff_n buffer input (connect directly to top-level port)
);
.DIFF_TERM("TRUE"), // Differential Termination
.IBUF_LOW_PWR("FALSE"), // Low power="TRUE", Highest performance="FALSE"
.IOSTANDARD("LVDS") // Specify the input I/O standard
) IBUFDS_adc_A (
.O (adc_A_pre), // Buffer output
.I (ADC_OUT_1A_P), // Diff_p buffer input (connect directly to top-level port)
.IB (ADC_OUT_1A_N) // Diff_n buffer input (connect directly to top-level port)
);
И разделяются на два бита в IDDR:
Код
IDDR #(
.DDR_CLK_EDGE("SAME_EDGE_PIPELINED"), // "OPPOSITE_EDGE", "SAME_EDGE"
// or "SAME_EDGE_PIPELINED"
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) IDDR_adc_A (
.Q1 (adc_A_out[0]), // 1-bit output for positive edge of clock
.Q2 (adc_A_out[1]), // 1-bit output for negative edge of clock
.C (clk_adc_dco), // 1-bit clock input
.CE (1'b1), // 1-bit clock enable input
.D (adc_A_pre), // 1-bit DDR data input
.R (1'b0), // 1-bit reset
.S (1'b0) // 1-bit set
);
.DDR_CLK_EDGE("SAME_EDGE_PIPELINED"), // "OPPOSITE_EDGE", "SAME_EDGE"
// or "SAME_EDGE_PIPELINED"
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) IDDR_adc_A (
.Q1 (adc_A_out[0]), // 1-bit output for positive edge of clock
.Q2 (adc_A_out[1]), // 1-bit output for negative edge of clock
.C (clk_adc_dco), // 1-bit clock input
.CE (1'b1), // 1-bit clock enable input
.D (adc_A_pre), // 1-bit DDR data input
.R (1'b0), // 1-bit reset
.S (1'b0) // 1-bit set
);
clk_adc_dco - клок, приходящий от ADC_DCO_P через BUFG.
При этом вылезает дикое несоответствие по холдам:

Подскажите как быть? Ведь наверняка кто-то делал такое.