component flash_update is
        port (
            clock                   : in  std_logic                     := 'X';             -- clk
            avmm_csr_addr           : in  std_logic                     := 'X';             -- address
            avmm_csr_read           : in  std_logic                     := 'X';             -- read
            avmm_csr_writedata      : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
            avmm_csr_write          : in  std_logic                     := 'X';             -- write
            avmm_csr_readdata       : out std_logic_vector(31 downto 0);                    -- readdata
            avmm_data_addr          : in  std_logic_vector(18 downto 0) := (others => 'X'); -- address
            avmm_data_read          : in  std_logic                     := 'X';             -- read
            avmm_data_writedata     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
            avmm_data_write         : in  std_logic                     := 'X';             -- write
            avmm_data_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
            avmm_data_waitrequest   : out std_logic;                                        -- waitrequest
            avmm_data_readdatavalid : out std_logic;                                        -- readdatavalid
            avmm_data_burstcount    : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- burstcount
            reset_n                 : in  std_logic                     := 'X'              -- reset_n
        );
    end component flash_update;

    u0 : component flash_update
        port map (
            clock                   => CONNECTED_TO_clock,                   --    clk.clk
            avmm_csr_addr           => CONNECTED_TO_avmm_csr_addr,           --    csr.address
            avmm_csr_read           => CONNECTED_TO_avmm_csr_read,           --       .read
            avmm_csr_writedata      => CONNECTED_TO_avmm_csr_writedata,      --       .writedata
            avmm_csr_write          => CONNECTED_TO_avmm_csr_write,          --       .write
            avmm_csr_readdata       => CONNECTED_TO_avmm_csr_readdata,       --       .readdata
            avmm_data_addr          => CONNECTED_TO_avmm_data_addr,          --   data.address
            avmm_data_read          => CONNECTED_TO_avmm_data_read,          --       .read
            avmm_data_writedata     => CONNECTED_TO_avmm_data_writedata,     --       .writedata
            avmm_data_write         => CONNECTED_TO_avmm_data_write,         --       .write
            avmm_data_readdata      => CONNECTED_TO_avmm_data_readdata,      --       .readdata
            avmm_data_waitrequest   => CONNECTED_TO_avmm_data_waitrequest,   --       .waitrequest
            avmm_data_readdatavalid => CONNECTED_TO_avmm_data_readdatavalid, --       .readdatavalid
            avmm_data_burstcount    => CONNECTED_TO_avmm_data_burstcount,    --       .burstcount
            reset_n                 => CONNECTED_TO_reset_n                  -- nreset.reset_n
        );

avmm_csr_addr
avmm_csr_read

avmm_data_addr
avmm_data_read

onchip_flash_0 : component altera_onchip_flash
    generic map (
    INIT_FILENAME                       => "",
    INIT_FILENAME_SIM                   => "",
    DEVICE_FAMILY                       => "MAX 10",
    PART_NAME                           => "10M50SAE144I7G",
    DEVICE_ID                           => "50",
    SECTOR1_START_ADDR                  => 0,
    SECTOR1_END_ADDR                    => 8191,
    SECTOR2_START_ADDR                  => 8192,
    SECTOR2_END_ADDR                    => 16383,
    SECTOR3_START_ADDR                  => 16384,
    SECTOR3_END_ADDR                    => 114687,
    SECTOR4_START_ADDR                  => 114688,
    SECTOR4_END_ADDR                    => 188415,
    SECTOR5_START_ADDR                  => 188416,
    SECTOR5_END_ADDR                    => 360447,
    MIN_VALID_ADDR                      => 0,
    MAX_VALID_ADDR                      => 360447,
    MIN_UFM_VALID_ADDR                  => 0,
    MAX_UFM_VALID_ADDR                  => 114687,
    SECTOR1_MAP                         => 1,
    SECTOR2_MAP                         => 2,
    SECTOR3_MAP                         => 3,
    SECTOR4_MAP                         => 4,
    SECTOR5_MAP                         => 5,
    ADDR_RANGE1_END_ADDR                => 360447,
    ADDR_RANGE1_OFFSET                  => 2048,
    ADDR_RANGE2_OFFSET                  => 0,
    AVMM_DATA_ADDR_WIDTH                => 19,
    AVMM_DATA_DATA_WIDTH                => 32,
    AVMM_DATA_BURSTCOUNT_WIDTH          => 4,
    SECTOR_READ_PROTECTION_MODE         => 4,
    FLASH_SEQ_READ_DATA_COUNT           => 4,
    FLASH_ADDR_ALIGNMENT_BITS           => 2,
    FLASH_READ_CYCLE_MAX_INDEX          => 5,
    FLASH_RESET_CYCLE_MAX_INDEX         => 14,
    FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX  => 72,
    FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX => 21000000,
    FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX => 18300,
    PARALLEL_MODE                       => true,
    READ_AND_WRITE_MODE                 => true,
    WRAPPING_BURST_MODE                 => false,
    IS_DUAL_BOOT                        => "False",
    IS_ERAM_SKIP                        => "True",
    IS_COMPRESSED_IMAGE                 => "False"