Код
module S6_ADC
(
input wire CLK_100,
output wire ADC_CLK,
input wire [7:0] ADC_IN,
output wire PWRDWN,
output wire [7:0] ADC_O
);
wire clk_to_ddr, clk_to_ddr_inv;
reg [7:0] adc_o_reg;
wire CLK_50, CLK_50_180, CLK_50_g;
//assign PWRDWN = ~LOCKED;
assign PWRDWN = 1'b0;
/*BUFG BUFG_inst (
.O(CLK_50_g), // 1-bit output: Clock buffer output
.I(CLK_100) // 1-bit input: Clock buffer input
);*/
BUFIO2 #(
.DIVIDE(2), // DIVCLK divider (1,3-8)
.DIVIDE_BYPASS("TRUE"), // Bypass the divider circuitry (TRUE/FALSE)
.I_INVERT("FALSE"), // Invert clock (TRUE/FALSE)
.USE_DOUBLER("TRUE") // Use doubler circuitry (TRUE/FALSE)
)
BUFIO2_diret
(
.DIVCLK(DIVCLK), // 1-bit output: Divided clock output
.IOCLK(clk_to_ddr), // 1-bit output: I/O output clock
.SERDESSTROBE(SERDESSTROBE), // 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
.I(CLK_100) // 1-bit input: Clock input (connect to IBUFG)
);
BUFIO2 #(
.DIVIDE(1), // DIVCLK divider (1,3-8)
.DIVIDE_BYPASS("TRUE"), // Bypass the divider circuitry (TRUE/FALSE)
.I_INVERT("TRUE"), // Invert clock (TRUE/FALSE)
.USE_DOUBLER("FALSE") // Use doubler circuitry (TRUE/FALSE)
)
BUFIO2_invert (
.DIVCLK(DIVCLK), // 1-bit output: Divided clock output
.IOCLK(clk_to_ddr_inv), // 1-bit output: I/O output clock
.SERDESSTROBE(SERDESSTROBE), // 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
.I(CLK_100) // 1-bit input: Clock input (connect to IBUFG)
);
ODDR2 #(
.DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
.SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_inst (
.Q(ADC_CLK), // 1-bit DDR output data
.C0(clk_to_ddr), // 1-bit clock input
.C1(clk_to_ddr_inv), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(1'b1), // 1-bit data input (associated with C0)
.D1(1'b0), // 1-bit data input (associated with C1)
.R(1'b0), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
always@(posedge CLK_100)
adc_o_reg <= ADC_IN;
assign ADC_O = adc_o_reg;
endmodule
(
input wire CLK_100,
output wire ADC_CLK,
input wire [7:0] ADC_IN,
output wire PWRDWN,
output wire [7:0] ADC_O
);
wire clk_to_ddr, clk_to_ddr_inv;
reg [7:0] adc_o_reg;
wire CLK_50, CLK_50_180, CLK_50_g;
//assign PWRDWN = ~LOCKED;
assign PWRDWN = 1'b0;
/*BUFG BUFG_inst (
.O(CLK_50_g), // 1-bit output: Clock buffer output
.I(CLK_100) // 1-bit input: Clock buffer input
);*/
BUFIO2 #(
.DIVIDE(2), // DIVCLK divider (1,3-8)
.DIVIDE_BYPASS("TRUE"), // Bypass the divider circuitry (TRUE/FALSE)
.I_INVERT("FALSE"), // Invert clock (TRUE/FALSE)
.USE_DOUBLER("TRUE") // Use doubler circuitry (TRUE/FALSE)
)
BUFIO2_diret
(
.DIVCLK(DIVCLK), // 1-bit output: Divided clock output
.IOCLK(clk_to_ddr), // 1-bit output: I/O output clock
.SERDESSTROBE(SERDESSTROBE), // 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
.I(CLK_100) // 1-bit input: Clock input (connect to IBUFG)
);
BUFIO2 #(
.DIVIDE(1), // DIVCLK divider (1,3-8)
.DIVIDE_BYPASS("TRUE"), // Bypass the divider circuitry (TRUE/FALSE)
.I_INVERT("TRUE"), // Invert clock (TRUE/FALSE)
.USE_DOUBLER("FALSE") // Use doubler circuitry (TRUE/FALSE)
)
BUFIO2_invert (
.DIVCLK(DIVCLK), // 1-bit output: Divided clock output
.IOCLK(clk_to_ddr_inv), // 1-bit output: I/O output clock
.SERDESSTROBE(SERDESSTROBE), // 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
.I(CLK_100) // 1-bit input: Clock input (connect to IBUFG)
);
ODDR2 #(
.DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
.SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_inst (
.Q(ADC_CLK), // 1-bit DDR output data
.C0(clk_to_ddr), // 1-bit clock input
.C1(clk_to_ddr_inv), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(1'b1), // 1-bit data input (associated with C0)
.D1(1'b0), // 1-bit data input (associated with C1)
.R(1'b0), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
always@(posedge CLK_100)
adc_o_reg <= ADC_IN;
assign ADC_O = adc_o_reg;
endmodule
В итоге получил от такую ошибку
Код
ERROR:Place:1136 - This design contains a global buffer instance,
<CLK_100_ibuf>, driving the net, <CLK_100_c>, that is driving the following
(first 30) non-clock load pins.
< PIN: BUFIO2_invert.I; >
< PIN: BUFIO2_diret.I; >
< PIN: BUFIO2_diret.IB; >
This is not a recommended design practice in Spartan-6 due to limitations in
the global routing that may cause excessive delay, skew or unroutable
situations. It is recommended to only use a BUFG resource to drive clock
loads. If you wish to override this recommendation, you may use the
CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
this message to a WARNING and allow your design to continue.
< PIN "CLK_100_ibuf.O" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
<CLK_100_ibuf>, driving the net, <CLK_100_c>, that is driving the following
(first 30) non-clock load pins.
< PIN: BUFIO2_invert.I; >
< PIN: BUFIO2_diret.I; >
< PIN: BUFIO2_diret.IB; >
This is not a recommended design practice in Spartan-6 due to limitations in
the global routing that may cause excessive delay, skew or unroutable
situations. It is recommended to only use a BUFG resource to drive clock
loads. If you wish to override this recommendation, you may use the
CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
this message to a WARNING and allow your design to continue.
< PIN "CLK_100_ibuf.O" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
Я добавил рекомендуемый констрейн:
Код
PIN "CLK_100_ibuf.O" CLOCK_DEDICATED_ROUTE = FALSE;
Но опять получил ошибку:
Код
ERROR:Place - ConstraintResolved NO placeable site for BUFIO2_invert
ERROR:Place - SIO has over-constrained componet BUFIO2_invert to have to
placeable sites. Constraints come from driver constraints AND load IO
constraints
ERROR:Place - SIO has over-constrained componet BUFIO2_invert to have to
placeable sites. Constraints come from driver constraints AND load IO
constraints
Что происходит?