ENTITY latch_OE IS
    port(    oe            : in std_logic;
            timer_in     : in natural    range 0    to 2**16-1;
            
            timer_out    : out natural    range 0    to 2**16-1  
            );
attribute clock_signal                : string;
attribute clock_signal of oe   : signal is "yes";
attribute period                      : string;
attribute period of oe         : signal is "15 ns";
end latch_OE;

architecture arh of latch_OE is
begin

process(oe)
  begin
     if (falling_edge(oe)) then
        timer_out <= timer_in;
    end if;
end process;
end arh;

library ieee;  
use ieee.std_logic_1164.all;  

entity flop is  
  port(C, D, CE  : in  std_logic;
      Q          : out std_logic);  
end flop;  
architecture archi of flop is  
  begin  
    process (C)  
      begin  
        if (C'event and C='1') then  
          if (CE='1') then  
            Q <= D;  
          end if;  
        end if;  
    end process;  
end archi;