library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity sinustest is
port(
clk: in STD_LOGIC;
rst: in STD_LOGIC;
dataz : out STD_LOGIC_VECTOR (15 downto 0);
data : out STD_LOGIC_VECTOR (15 downto 0));
);
end sinustest;

architecture Behavioral of sinustest is

type arr_type is array (0 to 16) of std_logic_vector(15 downto 0);
signal Y : arr_type;
signal X : arr_type;
signal Z : arr_type;
signal a : arr_type:=
(
"0011111111111111", "0010010111000111", "0001001111110110", "0000101000100010",
"0000010100010110", "0000001010001100", "0000000101000110", "0000000010100011",
"0000000001010001", "0000000000101001", "0000000000010100", "0000000000001010",
"0000000000000101", "0000000000000011", "0000000000000001", "0000000000000001","0000000000000000"); -- описание сигналов и фазового сдвига на каждый такт

type mode is (functioning1, functioning2);
signal state : mode;

begin
process (clk)
begin
if clk = '1' and clk'event then -- начальное значение (очевидно) по x y. стартовая отсечка вектора
if rst = '1' then
X(0) <= "0011111111111111";
Y(0) <= "0000000000000000";
state <= functioning1;
Z(0) <= "0000000000000000";
....
.... -- та дичь, где должно все происходить
end if;

dataz <= Z(16);
data <= Y (16);

end process;
end Behavioral;