library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

Entity sinyth is port(

clk : in std_logic;
resetn : in std_logic;
z : in std_logic_vector(15 downto 0);
x : in std_logic_vector(15 downto 0);
y : in std_logic_vector(15 downto 0);
sin : out std_logic_vector(15 downto 0));
end sinyth;

Architecture masive of sinyth is

type signed_array is ARRAY (natural range <>) of signed(15 downto 0);
constant tan_array: signed_array(0 to 16) := ("0110010001111011", "0011101101100100", "0001111101011100", "0000111111101100",
"0000011111111101", "0000001111111110", "0000000111111111", "0000000100000000",
"0000000010000000", "0000000001000000", "0000000000100000", "0000000000010000",
"0000000000001000", "0000000000000100", "0000000000000010", "0000000000000001", "0000000000000000");

signal x_array: signed_array (0 to 17) := (others => (others => '0'));
signal y_array: signed_array (0 to 17) := (others => (others => '0'));
signal z_array: signed_array (0 to 17) := (others => (others => '0'));

begin

process(clk)
begin
if resetn = '1' then
x_array <= (others => (others => '0'));
y_array <= (others => (others => '0'));
z_array <= (others => (others => '0'));
elsif rising_edge(clk) then
if signed(z) < to_signed(0, 16) then
x_array(x_array'low) <= signed(x) + signed(y);
y_array(y_array'low) <= signed(y) - signed(x);
z_array(z_array'low) <= signed(z) + tan_array(0);
else
x_array(x_array'low) <= signed(x) - signed(y);
y_array(y_array'low) <= signed(y) + signed(x);
z_array(z_array'low) <= signed(z) - tan_array(0);
end if;
for i in 1 to 14 loop
if z_array(i-1) < to_signed(0,16) then
x_array(i) <= x_array(i-1) + (y_array(i-1)/2**(i-1));
y_array(i) <= y_array(i-1) - (x_array(i-1)/2**(i-1));
z_array(i) <= z_array(i-1) + tan_array(i-1);
else
x_array(i) <= x_array(i-1) - (y_array(i-1)/2**(i-1));
y_array(i) <= y_array(i-1) + (x_array(i-1)/2**(i-1));
z_array(i) <= z_array(i-1) - tan_array(i);
end if;
end loop;
end if;
end process;
sin <= std_logic_vector(y_array(y_array'length(15 downto 0)));

end architecture masive;