Квартус выдает ошибку
Цитата
Error (10327): VHDL error at SMC.vhd(68): can't determine definition of operator ""sra"" -- found 0 possible definitions
Error (10411): VHDL Type Conversion error at SMC.vhd(68): can't determine type of object or expression near text or symbol "std_logic_vector"
Error (10411): VHDL Type Conversion error at SMC.vhd(68): can't determine type of object or expression near text or symbol "std_logic_vector"
в проекте стоит галочка использовать VHDL 2008
ошибка возникает в следующем описании:
Код
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
entity SMC is
generic ( M : natural := 32 );
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
en : in STD_LOGIC;
Tmax : in STD_LOGIC_VECTOR (31 downto 0); -- maximum timing
Nsegment : in STD_LOGIC_VECTOR (7 downto 0); -- total segment acceleration/deceleration
T0 : in STD_LOGIC_VECTOR (31 downto 0);
--Duty_cycle : in STD_LOGIC_VECTOR (15 downto 0);
--ready_period : out STD_LOGIC;
out_shim : out STD_LOGIC );
end SMC;
architecture Behavioral of SMC is
COMPONENT shim
generic ( N : natural := 3 );
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
en : in STD_LOGIC;
--load : in STD_LOGIC;
Period : in STD_LOGIC_VECTOR (N-1 downto 0);
Duty_cycle : in STD_LOGIC_VECTOR (N-1 downto 0);
ready_period : out STD_LOGIC;
out_shim : out STD_LOGIC );
END COMPONENT;
signal reg_period : STD_LOGIC_VECTOR (M-1 downto 0);
signal reg_duty_cycle : STD_LOGIC_VECTOR (M-1 downto 0);
signal count_period : STD_LOGIC_VECTOR (M-1 downto 0);
signal reg_number_of_steps : STD_LOGIC_VECTOR (M-1 downto 0);
signal reg_ready_period, reg_segment_ready : STD_LOGIC;
signal reg_en_shim, reg_load_shim : STD_LOGIC;
signal cnt_segments : STD_LOGIC_VECTOR (15 downto 0);
signal reg_number_of_segments : STD_LOGIC_VECTOR (M-1 downto 0);
signal cnt : STD_LOGIC_VECTOR (M-1 downto 0);
signal reg_duty_segment : STD_LOGIC_VECTOR (M-1 downto 0);
signal reg_ena_work : STD_LOGIC;
begin
shim_inst : shim
generic map (
N => M)
port map
(
clk => clk,
rst => rst,
en => reg_en_shim,
--load => reg_load_shim,
Period => reg_period,
Duty_cycle => reg_duty_cycle,
ready_period => reg_ready_period,
out_shim => out_shim
);
reg_en_shim <= '1';
reg_duty_cycle <= std_logic_vector (unsigned(reg_period) sra 1);
process (all)
begin
if rst = '1' then
count_period <= (others=>'0');
reg_period <= T0;
reg_number_of_segments <= std_logic_vector (unsigned(Tmax) sra conv_integer(Nsegment));
reg_duty_segment <= std_logic_vector (unsigned(Tmax) sra 0);
reg_segment_ready <= '0';
elsif(rising_edge(clk)) then
if reg_ena_work = '1' then
if cnt = reg_duty_segment then -- k
reg_period <= std_logic_vector (unsigned(reg_period) sra 1);
reg_segment_ready <= '1';
reg_duty_segment <= std_logic_vector (unsigned(Tmax) sra conv_integer(cnt_segments+1));
else
reg_segment_ready <= '0';
if reg_ready_period = '1' then
count_period <= count_period + "0000000000000001";
end if;
end if;
end if;
end if;
end process;
process (all)
begin
if rst = '1' then
cnt_segments <= (others=>'0');
cnt <= (others=>'0');
elsif(rising_edge(clk)) then
if reg_segment_ready = '1' then
cnt_segments <= cnt_segments + "0000000000000001";
cnt <= (others=>'0');
else
cnt <= cnt + 1;
end if;
end if;
end process;
process (all)
begin
if rst = '1' then
reg_ena_work <= '0';
elsif(rising_edge(clk)) then
if (cnt_segments = Nsegment) then
reg_ena_work <= '0';
elsif en = '1' then
reg_ena_work <= '1';
end if;
end if;
end process;
end Behavioral;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
entity shim is
generic ( N : natural := 3 );
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
en : in STD_LOGIC;
--load : in STD_LOGIC;
Period : in STD_LOGIC_VECTOR (N-1 downto 0);
Duty_cycle : in STD_LOGIC_VECTOR (N-1 downto 0);
ready_period : out STD_LOGIC;
out_shim : out STD_LOGIC );
end shim;
architecture Behavioral of shim is
signal count_shim : STD_LOGIC_VECTOR (N-1 downto 0);
signal reg_Period : STD_LOGIC_VECTOR (N-1 downto 0);
signal reg_Duty_cycle : STD_LOGIC_VECTOR (N-1 downto 0);
begin
process (all)
begin
if rst = '1' then
count_shim <= (others=>'0');
elsif(rising_edge(clk)) then
if en = '1' then
if count_shim = reg_Period then
ready_period <= '1';
count_shim <= (others=>'0');
else
count_shim <= count_shim + std_logic_vector( to_unsigned(1, count_shim'length ));
ready_period <= '0';
end if;
end if;
end if;
end process;
process (all)
begin
if rst = '1' then
out_shim <= '0';
elsif(rising_edge(clk)) then
if count_shim < reg_Duty_cycle then
out_shim <= '1';
else
out_shim <= '0';
end if;
end if;
end process;
process (all)
begin
if rst = '1' then
reg_Period <= (others=>'0');
reg_Duty_cycle <= (others=>'0');
elsif(rising_edge(clk)) then
if ready_period = '1' then
reg_Period <= Period;
reg_Duty_cycle <= Duty_cycle;
end if;
end if;
end process;
end Behavioral;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
entity SMC is
generic ( M : natural := 32 );
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
en : in STD_LOGIC;
Tmax : in STD_LOGIC_VECTOR (31 downto 0); -- maximum timing
Nsegment : in STD_LOGIC_VECTOR (7 downto 0); -- total segment acceleration/deceleration
T0 : in STD_LOGIC_VECTOR (31 downto 0);
--Duty_cycle : in STD_LOGIC_VECTOR (15 downto 0);
--ready_period : out STD_LOGIC;
out_shim : out STD_LOGIC );
end SMC;
architecture Behavioral of SMC is
COMPONENT shim
generic ( N : natural := 3 );
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
en : in STD_LOGIC;
--load : in STD_LOGIC;
Period : in STD_LOGIC_VECTOR (N-1 downto 0);
Duty_cycle : in STD_LOGIC_VECTOR (N-1 downto 0);
ready_period : out STD_LOGIC;
out_shim : out STD_LOGIC );
END COMPONENT;
signal reg_period : STD_LOGIC_VECTOR (M-1 downto 0);
signal reg_duty_cycle : STD_LOGIC_VECTOR (M-1 downto 0);
signal count_period : STD_LOGIC_VECTOR (M-1 downto 0);
signal reg_number_of_steps : STD_LOGIC_VECTOR (M-1 downto 0);
signal reg_ready_period, reg_segment_ready : STD_LOGIC;
signal reg_en_shim, reg_load_shim : STD_LOGIC;
signal cnt_segments : STD_LOGIC_VECTOR (15 downto 0);
signal reg_number_of_segments : STD_LOGIC_VECTOR (M-1 downto 0);
signal cnt : STD_LOGIC_VECTOR (M-1 downto 0);
signal reg_duty_segment : STD_LOGIC_VECTOR (M-1 downto 0);
signal reg_ena_work : STD_LOGIC;
begin
shim_inst : shim
generic map (
N => M)
port map
(
clk => clk,
rst => rst,
en => reg_en_shim,
--load => reg_load_shim,
Period => reg_period,
Duty_cycle => reg_duty_cycle,
ready_period => reg_ready_period,
out_shim => out_shim
);
reg_en_shim <= '1';
reg_duty_cycle <= std_logic_vector (unsigned(reg_period) sra 1);
process (all)
begin
if rst = '1' then
count_period <= (others=>'0');
reg_period <= T0;
reg_number_of_segments <= std_logic_vector (unsigned(Tmax) sra conv_integer(Nsegment));
reg_duty_segment <= std_logic_vector (unsigned(Tmax) sra 0);
reg_segment_ready <= '0';
elsif(rising_edge(clk)) then
if reg_ena_work = '1' then
if cnt = reg_duty_segment then -- k
reg_period <= std_logic_vector (unsigned(reg_period) sra 1);
reg_segment_ready <= '1';
reg_duty_segment <= std_logic_vector (unsigned(Tmax) sra conv_integer(cnt_segments+1));
else
reg_segment_ready <= '0';
if reg_ready_period = '1' then
count_period <= count_period + "0000000000000001";
end if;
end if;
end if;
end if;
end process;
process (all)
begin
if rst = '1' then
cnt_segments <= (others=>'0');
cnt <= (others=>'0');
elsif(rising_edge(clk)) then
if reg_segment_ready = '1' then
cnt_segments <= cnt_segments + "0000000000000001";
cnt <= (others=>'0');
else
cnt <= cnt + 1;
end if;
end if;
end process;
process (all)
begin
if rst = '1' then
reg_ena_work <= '0';
elsif(rising_edge(clk)) then
if (cnt_segments = Nsegment) then
reg_ena_work <= '0';
elsif en = '1' then
reg_ena_work <= '1';
end if;
end if;
end process;
end Behavioral;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
entity shim is
generic ( N : natural := 3 );
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
en : in STD_LOGIC;
--load : in STD_LOGIC;
Period : in STD_LOGIC_VECTOR (N-1 downto 0);
Duty_cycle : in STD_LOGIC_VECTOR (N-1 downto 0);
ready_period : out STD_LOGIC;
out_shim : out STD_LOGIC );
end shim;
architecture Behavioral of shim is
signal count_shim : STD_LOGIC_VECTOR (N-1 downto 0);
signal reg_Period : STD_LOGIC_VECTOR (N-1 downto 0);
signal reg_Duty_cycle : STD_LOGIC_VECTOR (N-1 downto 0);
begin
process (all)
begin
if rst = '1' then
count_shim <= (others=>'0');
elsif(rising_edge(clk)) then
if en = '1' then
if count_shim = reg_Period then
ready_period <= '1';
count_shim <= (others=>'0');
else
count_shim <= count_shim + std_logic_vector( to_unsigned(1, count_shim'length ));
ready_period <= '0';
end if;
end if;
end if;
end process;
process (all)
begin
if rst = '1' then
out_shim <= '0';
elsif(rising_edge(clk)) then
if count_shim < reg_Duty_cycle then
out_shim <= '1';
else
out_shim <= '0';
end if;
end if;
end process;
process (all)
begin
if rst = '1' then
reg_Period <= (others=>'0');
reg_Duty_cycle <= (others=>'0');
elsif(rising_edge(clk)) then
if ready_period = '1' then
reg_Period <= Period;
reg_Duty_cycle <= Duty_cycle;
end if;
end if;
end process;
end Behavioral;
ошибка ссылается на строку
reg_duty_cycle <= std_logic_vector (unsigned(reg_period) sra 1);
Моделсим 10.5 ошибок не выдает - моделирует...