entity ramdata is

    generic
    (
        DATA_WIDTH : natural;
        ADDR_WIDTH : natural
    );

    port
    (
        rclk    : in std_logic;
        wclk    : in std_logic;
        raddr    : in std_logic_vector (0 to ADDR_WIDTH - 1);
        waddr    : in std_logic_vector (0 to ADDR_WIDTH - 1);
        data    : in std_logic_vector((DATA_WIDTH-1) downto 0);
        we        : in std_logic;
        q        : out std_logic_vector((DATA_WIDTH -1) downto 0)
    );

end ramdata;

architecture behavioural of ramdata is

    subtype byte is std_logic_vector((DATA_WIDTH-1) downto 0);
    type memory is array(2**ADDR_WIDTH-1 downto 0) of byte;

    signal ram : memory;
    attribute ramstyle : string;
--    attribute ramstyle of ram : signal is "M512, no_rw_check";
    attribute ramstyle of ram : signal is "M9K, no_rw_check";
--    attribute ramstyle of ram : signal is "M-RAM";
--    attribute ramstyle of ram : signal is "MLAB, no_rw_check";

begin

    process(wclk)
    begin
    if(rising_edge(wclk)) then
        if(we = '0') then
            ram(conv_integer(waddr)) <= data;
        end if;
    end if;
    end process;

    process(rclk)
    begin
    if(rising_edge(rclk)) then
        if(we = '0') then
            q <= ram(conv_integer(raddr));
        else
            q <= (others => 'Z');
        end if;
    end if;
    end process;
    
end behavioural;

entity byte_enabled_simple_dual_port_ram is

    generic (
        ADDR_WIDTH : natural := 6;
        BYTE_WIDTH : natural := 8;
        BYTES : natural := 4);
  
    port (
        we, clk : in  std_logic;
        be      : in  std_logic_vector (BYTES - 1 downto 0);
        wdata   : in  std_logic_vector(BYTE_WIDTH - 1 downto 0);
        waddr   : in  integer range 0 to 2 ** ADDR_WIDTH -1;
        raddr   : in  integer range 0 to 2 ** ADDR_WIDTH - 1;
        q       : out std_logic_vector(BYTES*BYTE_WIDTH-1 downto 0));
end byte_enabled_simple_dual_port_ram;

architecture rtl of byte_enabled_simple_dual_port_ram is
    --  build up 2D array to hold the memory
    type word_t is array (0 to BYTES-1) of std_logic_vector(BYTE_WIDTH-1 downto 0);
    type ram_t is array (0 to 2 ** ADDR_WIDTH - 1) of word_t;
    -- delcare the RAM
    signal ram : ram_t;
    signal q_local : word_t;

begin  -- rtl
    -- Re-organize the read data from the RAM to match the output
    unpack: for i in 0 to BYTES - 1 generate    
        q(BYTE_WIDTH*(i+1) - 1 downto BYTE_WIDTH*i) <= q_local(i);
    end generate unpack;
        
    process(clk)
    begin
        if(rising_edge(clk)) then
            if(we = '1') then
                -- edit this code if using other than four bytes per word
                if(be(0) = '1') then
                    ram(waddr)(0) <= wdata;
                end if;
                if be(1) = '1' then
                    ram(waddr)(1) <= wdata;
                end if;
                if be(2) = '1' then
                    ram(waddr)(2) <= wdata;
                end if;
                if be(3) = '1' then
                    ram(waddr)(3) <= wdata;
                end if;
            end if;
            q_local <= ram(raddr);
        end if;
    end process;  
end rtl;