library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity mem_buf_kadr is
    port
        (
        -- in side
        DIN             : in     std_logic_vector (15 downto 0);
        WR             : in     std_logic;
        clk_in        : in std_logic;
        adr_str_in     : std_logic_vector (8 downto 0);
        --- out side
        clk_out        : in std_logic;
        DOUT             : out std_logic_vector (15 downto 0);
        adr_str_out    : in std_logic_vector (8 downto 0);
        adr_col_out    : in std_logic_vector (8 downto 0);
        -- debug
        deb_dat    : out std_logic_vector (7 downto 0)
        );
end mem_buf_kadr;

architecture mem_buf_kadr_a of mem_buf_kadr is
    -- signal
    
    signal ct_pix: std_logic_vector(8 downto 0):=(others=>'0');
    signal adr_col_in: std_logic_vector(8 downto 0):=(others=>'0');
    signal wrz,wr0,wr1,wr2: std_logic;
    signal DOUT0,DOUT1,DOUT2: std_logic_vector(15 downto 0):=(others=>'0');
    
    component block_ozu IS
    PORT
    (
        data            : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
        rdaddress    : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
        rdclock        : IN STD_LOGIC;
        wraddress    : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
        wrclock        : IN STD_LOGIC  := '1';
        wren            : IN STD_LOGIC  := '0';
        q                : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
    );
END component;

begin
    
u0:block_ozu
port map (
        
        rdaddress (8 downto 0)    =>adr_col_out,
        rdclock                        =>clk_out,
        q                                =>DOUT0,
        
        data                            => "0010000000000000",--DIN,
        wraddress(8 downto 0)    =>adr_col_in,
        wrclock                        =>clk_out,
        wren                            =>WR
        
        );
        
--u1:ram_kadr
--port map (
--        data            =>DIN,
--        rdaddress (8 downto 0)=>adr_col_out,
--        rdaddress (15 downto 9)=>adr_str_out(6 downto 0),
--        rdclock    =>clk_out,
--        
--        wraddress    (8 downto 0)=>adr_col_in,
--        wraddress    (15 downto 9)=>adr_str_in(6 downto 0),
--        wrclock        =>clk_out,
--        wren            =>WR1,
--        q                =>DOUT1
--        );

--u2:ram_kadr
--port map (
--        data            =>DIN,
--        rdaddress (8 downto 0)=>adr_col_out,
--        rdaddress (15 downto 9)=>adr_str_out(6 downto 0),
--        rdclock    =>clk_out,
--    
--        wraddress    (8 downto 0)=>adr_col_in,
--        wraddress    (15 downto 9)=>adr_str_in(6 downto 0),
--        wrclock        =>clk_out,
--        wren            =>WR2,
--        q                =>DOUT2
--        );


    process (clk_in)
    begin
        if (clk_in'event and clk_in='1') then
            if wr='1' then
                if ct_pix="101111111" then
                    ct_pix<=(others=>'0');
                else -- ct_pix="101111111"
                    ct_pix<=ct_pix+1;
                end if; -- ct_pix="101111111"
            end if; --wr=1
            --wrz<=wr;
        end if; --(clk'event and clk='1')
    end process;
    adr_col_in<=ct_pix;    

--wr0<=wr and (not adr_str_in(8)) and (not adr_str_in(7));
--wr1<=wr and (not adr_str_in(8)) and (adr_str_in(7));
--wr2<=wr and (adr_str_in(8)) and (not adr_str_in(7));

process (clk_out)
begin
  if (clk_out'event and clk_out='1') then
    if (adr_str_out(8 downto 7)="00") then
     DOUT<=DOUT0;
     elsif (adr_str_out(8 downto 7)="01") then
     DOUT<="0000000000000000";--DOUT1;
     else
     DOUT<="0000000000000000";--DOUT2;
     end if; -- adr_str_out
     end if; --clk
end process;
    
    deb_dat<=adr_col_in(8 downto 1);
            
end mem_buf_kadr_a;