library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use std.textio.all;

entity RAM_DP is
generic (
width :natural := 8; -- Width of data[] and q[] ports.
widthad :natural := 8 -- Width of the address port.
);

port (
clk : in std_logic := '0';
wren : in std_logic := '0';
rdaddress : in std_logic_vector(widthad-1 downto 0);
wraddress : in std_logic_vector(widthad-1 downto 0);
data : in std_logic_vector(width-1 downto 0);
---
q : out std_logic_vector(width-1 downto 0)
);
end RAM_DP;

architecture TELESH of RAM_DP is
--
signal rdaddress_reg : std_logic_vector(widthad-1 downto 0) := (others => '0');
signal wraddress_reg : std_logic_vector(widthad-1 downto 0) := (others => '0');
signal data_reg : std_logic_vector(width-1 downto 0) := (others => '0');
signal q_tmp : std_logic_vector(width-1 downto 0);
signal wren_reg : std_logic := '1';

--type memory is array (((2**widthad) - 1) downto 0) of std_logic_vector(width-1 downto 0);
--signal RAM : memory;
begin

input_register: process(clk)
begin
if (rising_edge(clk)) then

rdaddress_reg <= rdaddress;
wraddress_reg <= wraddress;
data_reg <= data;
wren_reg <= wren;

end if;
end process input_register;

write_read: process(clk, wren_reg, data_reg, q_tmp)

type memory is array (((2**widthad) - 1) downto 0) of std_logic_vector(width-1 downto 0);
variable RAM : memory;
variable i : integer :=0;

begin

-- initialize RAM

for i in RAM'low to RAM'high loop

RAM(i) := (conv_std_logic_vector(i,width));
-- RAM(i) <= (conv_std_logic_vector(i,width));
-- RAM(i) := (others => '0');

end loop;


if wren_reg = '1' then
if (rising_edge(clk)) then
RAM(conv_integer(wraddress_reg)) := data_reg;
-- RAM(conv_integer(wraddress_reg)) <= data_reg;
end if;
end if;

if (rising_edge(clk)) then
q_tmp <= RAM(conv_integer(rdaddress_reg));
end if;

end process write_read;

q <= q_tmp;

end TELESH;


---------------


-------------------------------------------------------------------------------
--
-- Title : Test Bench for ram_dp
-- Design : UROK2
-- Author : SHUR!K
-- Company : SI
--
-------------------------------------------------------------------------------
--
-- File : $DSN\src\TestBench\ram_dp_TB.vhd
-- Generated : 31.10.2017, 14:46
-- From : f:\ModelSimWork\UROK2\RAM_DP.vhd
-- By : Active-HDL Built-in Test Bench Generator ver. 1.2s
--
-------------------------------------------------------------------------------
--
-- Description : Automatically generated Test Bench for ram_dp_tb
--
-------------------------------------------------------------------------------

library ieee;
use std.textio.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;

-- Add your library and packages declaration here ...

entity ram_dp_tb is
-- Generic declarations of the tested unit
generic(
width : NATURAL := 8;
widthad : NATURAL := 8 );
end ram_dp_tb;

architecture TB_ARCHITECTURE of ram_dp_tb is
-- Component declaration of the tested unit
component ram_dp
generic(
width : NATURAL := 8;
widthad : NATURAL := 8 );
port(
clk : in std_logic;
wren : in std_logic;
rdaddress : in std_logic_vector((widthad-1) downto 0);
wraddress : in std_logic_vector((widthad-1) downto 0);
data : in std_logic_vector((width-1) downto 0);
q : out std_logic_vector((width-1) downto 0) );
end component;

-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal clk : std_logic;
signal wren : std_logic := '0';
signal rdaddress : std_logic_vector((widthad-1) downto 0) := "00000000";
signal wraddress : std_logic_vector((widthad-1) downto 0) := "00000000";
signal data : std_logic_vector((width-1) downto 0) := "00000000";
-- Observed signals - signals mapped to the output ports of tested entity
signal q : std_logic_vector((width-1) downto 0);

-- Add your code here ...

begin

-- Unit Under Test port map
UUT : ram_dp
generic map (
width => width,
widthad => widthad
)

port map (
clk => clk,
wren => wren,
rdaddress => rdaddress,
wraddress => wraddress,
data => data,
q => q
);

-- Add your stimulus here ...

write: process
begin
wait for 500 ns;

wren <= '1';
data <= "01101001";
wraddress <= "00001001";

wait for 200 ns;

wren <= '0';
data <= "00000000";
wraddress <= "00000000";

wait for 200 ns;

wren <= '1';
data <= "01101010";
wraddress <= "00001001";

wait for 200 ns;

wren <= '0';
data <= "00000000";
wraddress <= "00000000";

wait for 400 ns;

wren <= '0';
rdaddress <= "00001001";

wait;

end process write ;



clock: process
begin
clk <= '1';
wait for 100 ns;
clk <= '0';
wait for 100 ns;
end process clock ;

end TB_ARCHITECTURE;

configuration TESTBENCH_FOR_ram_dp of ram_dp_tb is
for TB_ARCHITECTURE
for UUT : ram_dp
use entity work.ram_dp(telesh);
end for;
end for;
end TESTBENCH_FOR_ram_dp;