;==========================================================================
;
;   IMPORTANT: For the PIC18 devices, the __CONFIG directive has been
;              superseded by the CONFIG directive.  The following settings
;              are available for this device.
;
;   PLL Prescaler Selection bits:
;     PLLDIV = 1           No prescale (4 MHz oscillator input drives PLL directly)
;     PLLDIV = 2           Divide by 2 (8 MHz oscillator input)
;     PLLDIV = 3           Divide by 3 (12 MHz oscillator input)
;     PLLDIV = 4           Divide by 4 (16 MHz oscillator input)
;     PLLDIV = 5           Divide by 5 (20 MHz oscillator input)
;     PLLDIV = 6           Divide by 6 (24 MHz oscillator input)
;     PLLDIV = 10          Divide by 10 (40 MHz oscillator input)
;     PLLDIV = 12          Divide by 12 (48 MHz oscillator input)
;
;   System Clock Postscaler Selection bits:
;     CPUDIV = OSC1_PLL2   [Primary Oscillator Src: /1][96 MHz PLL Src: /2]
;     CPUDIV = OSC2_PLL3   [Primary Oscillator Src: /2][96 MHz PLL Src: /3]
;     CPUDIV = OSC3_PLL4   [Primary Oscillator Src: /3][96 MHz PLL Src: /4]
;     CPUDIV = OSC4_PLL6   [Primary Oscillator Src: /4][96 MHz PLL Src: /6]
;
;   USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1):
;     USBDIV = 1           USB clock source comes directly from the primary oscillator block with no postscale
;     USBDIV = 2           USB clock source comes from the 96 MHz PLL divided by 2

......