library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity pulse_len_measure is
generic (
  N                           : integer:=8);
port (
  i_clk                       : in  std_logic;
  i_rstb                      : in  std_logic;
  i_input                     : in  std_logic;
  o_pulse_len_hi              : out std_logic_vector(N-1 downto 0);
  o_pulse_len_lo              : out std_logic_vector(N-1 downto 0));
end pulse_len_measure;

architecture rtl of pulse_len_measure is
constant C_MAX_COUNT           : unsigned(N-1 downto 0):=(others=>'1');
signal r_count_hi_ena          : std_logic;
signal r_count_hi              : unsigned(N-1 downto 0);
signal r_count_lo              : unsigned(N-1 downto 0);
signal r_count_lo_ena          : std_logic;
signal r_rise                  : std_logic;
signal r_fall                  : std_logic;
signal p_input                 : std_logic_vector(0 to 2); -- input pipe

begin

p_edge_detector : process(i_clk,i_rstb)
begin
  if(i_rstb='0') then
    r_rise       <= '0';
    r_fall       <= '0';
    p_input      <= (others=>'0');
  elsif(rising_edge(i_clk)) then
    r_rise       <= not p_input(2) and p_input(1);
    r_fall       <= not p_input(1) and p_input(2);
    p_input      <= i_input&p_input(0 to p_input'length-2);
  end if;
end process p_edge_detector;

p_count_hi : process(i_clk,i_rstb)
begin
  if(i_rstb='0') then
    r_count_hi_ena  <= '0';
    r_count_hi      <= to_unsigned(1,N);
    o_pulse_len_hi  <= (others=>'0');
  elsif(rising_edge(i_clk)) then
    if(r_rise='1') then
      r_count_hi_ena  <= '1';
    elsif(r_fall='1') then
      r_count_hi_ena  <= '0';
      o_pulse_len_hi  <= std_logic_vector(r_count_hi);
    end if;

    if(r_count_hi_ena='1') then
      if(r_count_hi<C_MAX_COUNT)then
        r_count_hi      <= r_count_hi + 1;
      end if;
    else
      r_count_hi      <= to_unsigned(1,N);
    end if;
  end if;
end process p_count_hi;

p_count_lo : process(i_clk,i_rstb)
begin
  if(i_rstb='0') then
    r_count_lo_ena  <= '0';
    r_count_lo      <= to_unsigned(1,N);
    o_pulse_len_lo  <= (others=>'0');
  elsif(rising_edge(i_clk)) then
    if(r_fall='1') then
      r_count_lo_ena  <= '1';
    elsif(r_rise='1') then
      r_count_lo_ena  <= '0';
      o_pulse_len_lo  <= std_logic_vector(r_count_lo);
    end if;

    if(r_count_lo_ena='1') then
      if(r_count_lo<C_MAX_COUNT) then
        r_count_lo      <= r_count_lo + 1;
      end if;
    else
      r_count_lo      <= to_unsigned(1,N);
    end if;
  end if;
end process p_count_lo;

end rtl;