module add_three_numbers
(
input clock,
input [7:0] A,
input [7:0] B,
input [7:0] C,
input [7:0] D,
output [7:0] sum
);

reg [7:0] reg_A, reg_B, reg_C, reg_D;
reg [7:0] reg_sum;

reg [7:0] sum1, sum2;
reg [7:0] sum3;


always@(posedge clock)begin
reg_A <= A;
reg_B <= B;
reg_C <= C;
reg_D <= D;
end

always@(posedge clock)begin
sum1 <= reg_A + reg_B;
sum2 <= reg_C + reg_D;
sum3 <= sum1 + sum2;
end


always@(posedge clock)begin
reg_sum <= sum3;
end

assign sum = reg_sum;

endmodule

create_clock -name {clock} -period 400Mhz [get_ports {clock}]

set_input_delay -clock clock -min 0.8 [get_ports {A[*]}]
set_input_delay -clock clock -max 1.6 [get_ports {A[*]}]
...
set_output_delay -clock clock -min 0.0 [get_ports {sum[*]}]
set_output_delay -clock clock -max 0.2 [get_ports {sum[*]}]

create_clock -name {clock} -period 400Mhz [get_ports {clock}]

set_input_delay -clock [get_clocks clock] -min 0.8 [get_ports A[*]]
set_input_delay -clock [get_clocks clock] -max 1.6 [get_ports A[*]] -add_delay

set_input_delay -clock [get_clocks clock] -min 0.8 [get_ports B[*]]
set_input_delay -clock [get_clocks clock] -max 1.6 [get_ports B[*]] -add_delay

set_input_delay -clock [get_clocks clock] -min 0.8 [get_ports C[*]]
set_input_delay -clock [get_clocks clock] -max 1.6 [get_ports C[*]] -add_delay

set_input_delay -clock [get_clocks clock] -min 0.8 [get_ports D[*]]
set_input_delay -clock [get_clocks clock] -max 1.6 [get_ports D[*]] -add_delay

set_output_delay -clock [get_clocks clock] -min 0.0 [get_ports sum[*]]
set_output_delay -clock [get_clocks clock] -max 0.2 [get_ports sum[*]] -add_delay

derive_clock_uncertainty

module add_three_numbers
(
input clock,
input [7:0] A,
input [7:0] B,
input [7:0] C,
input [7:0] D,
output [7:0] sum
);

reg [7:0] reg_A, reg_B, reg_C, reg_D;
reg [7:0] reg_sum;

reg [7:0] sum1, sum2;
reg [7:0] sum3;


always@(posedge clock)begin
reg_A <= A;
reg_B <= B;
reg_C <= C;
reg_D <= D;
end

always@(posedge clock)begin
sum1 <= reg_A + reg_B;
sum2 <= reg_C + reg_D;
sum3 <= sum1 + sum2;
end


// always@(posedge clock)begin
// reg_sum <= sum3;
// end

// assign sum = reg_sum;
assign sum = sum3;

endmodule

# -------------------------------------------------------------------------- #
#
# Copyright © 2016 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 16.1.0 Build 196 10/24/2016 SJ Standard Edition
# Date created = 11:20:56 January 12, 2018
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# test_00_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CEBA4F17I7
set_global_assignment -name TOP_LEVEL_ENTITY add_three_numbers
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:20:56 JANUARY 12, 2018"
set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Standard Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name VERILOG_FILE top.v
set_global_assignment -name SDC_FILE top.sdc
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_A3 -to A[0]
set_location_assignment PIN_A4 -to A[1]
set_location_assignment PIN_A5 -to A[2]
set_location_assignment PIN_A7 -to A[3]
set_location_assignment PIN_A8 -to A[4]
set_location_assignment PIN_A9 -to A[5]
set_location_assignment PIN_B6 -to A[6]
set_location_assignment PIN_B7 -to A[7]
set_location_assignment PIN_B10 -to B[0]
set_location_assignment PIN_C9 -to B[1]
set_location_assignment PIN_C10 -to B[2]
set_location_assignment PIN_B11 -to B[3]
set_location_assignment PIN_C11 -to B[4]
set_location_assignment PIN_D11 -to B[5]
set_location_assignment PIN_A12 -to B[6]
set_location_assignment PIN_A13 -to B[7]
set_location_assignment PIN_B16 -to C[0]
set_location_assignment PIN_C16 -to C[1]
set_location_assignment PIN_D16 -to C[2]
set_location_assignment PIN_E16 -to C[3]
set_location_assignment PIN_C15 -to C[4]
set_location_assignment PIN_D14 -to C[5]
set_location_assignment PIN_D13 -to C[6]
set_location_assignment PIN_F15 -to C[7]
set_location_assignment PIN_G16 -to sum[0]
set_location_assignment PIN_H16 -to sum[1]
set_location_assignment PIN_J16 -to sum[2]
set_location_assignment PIN_G15 -to sum[3]
set_location_assignment PIN_K16 -to sum[4]
set_location_assignment PIN_K15 -to sum[5]
set_location_assignment PIN_L15 -to sum[6]
set_location_assignment PIN_L14 -to sum[7]
set_location_assignment PIN_J14 -to sum[8]
set_location_assignment PIN_J12 -to sum[9]
set_location_assignment PIN_F12 -to clock
set_location_assignment PIN_T15 -to D[0]
set_location_assignment PIN_T14 -to D[1]
set_location_assignment PIN_R16 -to D[2]
set_location_assignment PIN_R14 -to D[3]
set_location_assignment PIN_P16 -to D[4]
set_location_assignment PIN_P14 -to D[5]
set_location_assignment PIN_P13 -to D[6]
set_location_assignment PIN_M13 -to D[7]
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top