library ieee;
    use ieee.std_logic_1164.all;

entity pattern_detector is
    port
    (
        clk                     : in  std_logic;                          
        analyse_data            : in  std_logic_vector(9 downto 0);        -- данные для анализа
        pattern_found           : out std_logic                            -- Флаг найденного тестового паттерна
    );
end entity;

architecture RTL of pattern_detector is
    constant pattern0       : std_logic_vector(9 downto 0) := "1101010100";  -- тестовое слово  
    constant pattern1       : std_logic_vector(9 downto 0) := "0010101011";  -- тестовое слово  
    constant pattern2       : std_logic_vector(9 downto 0) := "0101010100";  -- тестовое слово
    constant pattern3       : std_logic_vector(9 downto 0) := "1010101011";  -- тестовое слово
begin

    --=====================================================================
    -- Процесс анализирования тестовых слов
    --=====================================================================
    pattern_detector_proc : process(clk)
    begin
        if (rising_edge(clk)) then
            case analyse_data is                  
                when pattern0 => pattern_found <= '1';
                when pattern1 => pattern_found <= '1';
                when pattern2 => pattern_found <= '1';
                when pattern3 => pattern_found <= '1';
                when others   => pattern_found <= '0';
            end case;
        end if;
    end process;
end architecture;

1_101010100
0_101010100

0_010101011
1_010101011