/* FPGA загружается процессором с помощью SPI */
static void board_fpga_loader_PS(void)
{
#if (WITHSPIHW && WITHSPI16BIT) // for skip in test configurations

#if (CTLSTYLE_RAVENDSP_V3 && ! WITHUSEDUALWATCH) && (DDS1_CLK_MUL == 10)
#include "rbf/rbfimage_v3_pll.h"
#elif (CTLSTYLE_RAVENDSP_V3 && ! WITHUSEDUALWATCH) && (DDS1_CLK_MUL == 1)
#include "rbf/rbfimage_v3.h"
#elif (CTLSTYLE_RAVENDSP_V4 && ! WITHUSEDUALWATCH) && (DDS1_CLK_MUL == 10)
#include "rbf/rbfimage_v4_pll.h"
#elif (CTLSTYLE_RAVENDSP_V4 && ! WITHUSEDUALWATCH) && (DDS1_CLK_MUL == 1)
#include "rbf/rbfimage_v4.h"
#elif CTLSTYLE_RAVENDSP_V5 && (DDS1_CLK_MUL == 10)
#include "rbf/rbfimage_v5_2ch_pll.h" // CTLSTYLE_RAVENDSP_V5 with 12.288 osc
#elif CTLSTYLE_RAVENDSP_V5 && (DDS1_CLK_MUL == 1) && WITHOPERA4BEACON
#include "rbf/rbfimage_v5_2ch_opera4.h" // CTLSTYLE_RAVENDSP_V5
#elif CTLSTYLE_RAVENDSP_V5 && (DDS1_CLK_MUL == 1)
#include "rbf/rbfimage_v5_2ch.h" // CTLSTYLE_RAVENDSP_V5
#elif CTLSTYLE_RAVENDSP_V6 && (DDS1_CLK_MUL == 1)
#include "rbf/rbfimage_v6_2ch.h" // CTLSTYLE_RAVENDSP_V6
#elif CTLSTYLE_RAVENDSP_V7 && (DDS1_CLK_MUL == 1)
#include "rbf/rbfimage_v7_2ch.h" // CTLSTYLE_RAVENDSP_V7
#elif CTLSTYLE_RAVENDSP_V8 && (DDS1_CLK_MUL == 1)
#include "rbf/rbfimage_v8.h"
#elif CTLSTYLE_RAVENDSP_V9 && (DDS1_CLK_MUL == 1)
#include "rbf/rbfimage_v7renesas_2ch.h"
#elif CTLSTYLE_RAVENDSP_V2 && (DDS1_CLK_MUL == 1) && WITHRTS192
#include "rbf/rbfimage_v8renesas_2ch.h"
#elif CTLSTYLE_RAVENDSP_V2 && (DDS1_CLK_MUL == 1)
#include "rbf/rbfimage_v8renesas96k_2ch.h"
#elif CTLSTYLE_STORCH_V1 && ! WITHUSEDUALWATCH && (DDS1_CLK_MUL == 1)
#include "rbf/rbfimage_v7_1ch.h" //
#elif CTLSTYLE_STORCH_V1 && (DDS1_CLK_MUL == 1)
#include "rbf/rbfimage_v7_2ch.h" // same as CTLSTYLE_RAVENDSP_V7
#elif CTLSTYLE_STORCH_V2 && ! WITHUSEDUALWATCH && (DDS1_CLK_MUL == 1)
#include "rbf/rbfimage_v7_1ch.h" //
#elif CTLSTYLE_STORCH_V2 && (DDS1_CLK_MUL == 1)
#include "rbf/rbfimage_v7_2ch.h" // same as CTLSTYLE_RAVENDSP_V7
#elif CTLSTYLE_STORCH_V3 && ! WITHUSEDUALWATCH && (DDS1_CLK_MUL == 1)
#include "rbf/rbfimage_v7_1ch.h" //
#elif CTLSTYLE_STORCH_V3 && (DDS1_CLK_MUL == 1)
#include "rbf/rbfimage_v7_2ch.h" // same as CTLSTYLE_RAVENDSP_V7
#elif CTLSTYLE_STORCH_V4 && ! WITHUSEDUALWATCH && (DDS1_CLK_MUL == 1) // modem v2
#include "rbf/rbfimage_v7_1ch.h" //
//#elif CTLSTYLE_STORCH_V4 && (DDS1_CLK_MUL == 1) // modem v2
// #include "rbf/rbfimage_v7_2ch.h" // same as CTLSTYLE_RAVENDSP_V7
#elif CTLSTYLE_STORCH_V5 && ! WITHUSEDUALWATCH && (DDS1_CLK_MUL == 1) // mini
#include "rbf/rbfimage_v7_1ch.h" //
#elif CTLSTYLE_STORCH_V5 && (DDS1_CLK_MUL == 1) // mini
#include "rbf/rbfimage_v7a_2ch.h" // same as CTLSTYLE_RAVENDSP_V7
#elif CTLSTYLE_STORCH_V6 && ! WITHUSEDUALWATCH && (DDS1_CLK_MUL == 1) // mini
#include "rbf/rbfimage_v7_1ch.h" //
#elif CTLSTYLE_STORCH_V6 && (DDS1_CLK_MUL == 1) // mini
#include "rbf/rbfimage_v7a_2ch.h" // same as CTLSTYLE_STORCH_V6
#elif CTLSTYLE_OLEG4Z_V1 && (DDS1_CLK_MUL == 1)
#include "rbf/rbfimage_oleg4z.h" // same as CTLSTYLE_RAVENDSP_V7, 1 RX & WFM
#else
#error Missing FPGA image file
#endif

restart:
;
unsigned long w = 1000;
do {
debug_printf_P(PSTR("fpga: board_fpga_loader_PS start\n"));
const size_t rbflength = sizeof rbfimage / sizeof rbfimage [0];
/* After power up, the Cyclone IV device holds nSTATUS low during POR delay. */

FPGA_NCONFIG_PORT_S(FPGA_NCONFIG_BIT);
local_delay_ms(1);
/* 1) Выставить "1" на nCONFIG */
//debug_printf_P(PSTR("fpga: FPGA_NCONFIG_BIT=1\n"));
FPGA_NCONFIG_PORT_C(FPGA_NCONFIG_BIT);
/* x) Дождаться "0" на nSTATUS */
//debug_printf_P(PSTR("fpga: waiting for FPGA_NSTATUS_BIT==0\n"));
while (board_fpga_get_NSTATUS() != 0)
{
local_delay_ms(1);
if (-- w == 0)
goto restart;
}
FPGA_NCONFIG_PORT_S(FPGA_NCONFIG_BIT);
/* 2) Дождаться "1" на nSTATUS */
//debug_printf_P(PSTR("fpga: waiting for FPGA_NSTATUS_BIT==1\n"));
while (board_fpga_get_NSTATUS() == 0)
{
local_delay_ms(1);
if (-- w == 0)
goto restart;
}
/* 3) Выдать байты (бладший бит .rbf файла первым) */
//debug_printf_P(PSTR("fpga: start sending RBF image (%lu of 16-bit words)\n"), rbflength);
if (rbflength != 0)
{
unsigned wcd = 0;
size_t n = rbflength - 1;
const uint16_t * p = rbfimage;
//

hardware_spi_connect_b16(SPIC_SPEEDUFAST, SPIC_MODE3);

hardware_spi_b16_p1(* p ++);
while (n --)
{
if (board_fpga_get_CONF_DONE() != 0)
{
//debug_printf_P(PSTR("fpga: Unexpected state of CONF_DONE==1\n"));
break;
}
hardware_spi_b16_p2(* p ++);
}

//debug_printf_P(PSTR("fpga: done sending RBF image, waiting for CONF_DONE==1\n"));
/* 4) Дождаться "1" на CONF_DONE */
while (board_fpga_get_CONF_DONE() == 0)
{
++ wcd;
hardware_spi_b16_p2(0xffff);
}

hardware_spi_complete_b16();

hardware_spi_disconnect();

//debug_printf_P(PSTR("fpga: CONF_DONE asserted, wcd=%u\n"), wcd);
/*
After the configuration data is accepted and CONF_DONE goes
high, Cyclone IV devices require 3,192 clock cycles to initialize properly and enter
user mode.
*/
}
} while (board_fpga_get_NSTATUS() == 0); // если ошибка - повторяем
//debug_printf_P(PSTR("fpga: board_fpga_loader_PS done\n"));
/* проверяем, проинициализировалась ли FPGA (вошла в user mode). */
while (HARDWARE_FPGA_IS_USER_MODE() == 0)
{
local_delay_ms(1);
if (-- w == 0)
goto restart;
}
debug_printf_P(PSTR("fpga: board_fpga_loader_PS: usermode okay\n"));
#endif /* (WITHSPIHW && WITHSPI16BIT) */ // for skip in test configurations
}

quartus_cpf -c test1.sof test1.rbf