inline void SysClk_init(void)
{
/* Reset and disable RCC Interrupts, on HSI and HSE, switch to HSI */
RCC->CIR = 0xFFFF0000;
RCC->CR |= RCC_CR_HSION | RCC_CR_HSEON;
while ((RCC->CR & RCC_CR_HSIRDY) != RCC_CR_HSIRDY) { }
RCC->CFGR &= ~RCC_CFGR_SW;
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) { }

/* Off PLL, set clock dividers */
RCC->CR &= ~RCC_CR_PLLON;
RCC->CFGR =
RCC_CFGR_SW_0 * 0 | // System clock Switch: HSI
RCC_CFGR_HPRE_0 * 0 | // AHB prescaler: SYSCLK / 1 = 120 MHz
RCC_CFGR_PPRE1_0 * 5 | // APB1 prescaler: AHB / 4 = 30 MHz
RCC_CFGR_PPRE2_0 * 4 | // APB2 prescaler: AHB / 2 = 60 MHz
RCC_CFGR_RTCPRE_0 * 0 | // HSE division factor for RTC clock
RCC_CFGR_MCO1_0 * 3 | // MCO1: PLL clock selected
RCC_CFGR_I2SSRC * 0 | // I2S clock selection: PLLI2S clock used
RCC_CFGR_MCO1PRE_0 * 5 | // MCO1 prescaler: PLL / 3 = 40 MHz
RCC_CFGR_MCO2PRE_0 * 5 | // MCO2 prescaler: SYSCLK / 3 = 40 MHz
RCC_CFGR_MCO2_0 * 0; // MCO2: System clock selected
RCC->PLLCFGR =
RCC_PLLCFGR_PLLM_0 * 4 | // Div factor for PLL input: HSE / 4 = 2 MHz
RCC_PLLCFGR_PLLN_0 * 120 | // PLL mult factor for VCO: 240 MHz
RCC_PLLCFGR_PLLP_0 * 0 | // PLL div factor for system clock: VCO / 2 = 120 MHz
RCC_PLLCFGR_PLLSRC * 1 | // PLL and PLLI2S clock source: HSE
RCC_PLLCFGR_PLLQ_0 * 5; // PLL div factor for USB OTG FS...: VCO / 5 = 48 MHz

/* Check HSE on, on PLL, set Flash Latency */
while ((RCC->CR & RCC_CR_HSERDY) != RCC_CR_HSERDY) { }
RCC->CR |= RCC_CR_PLLON;
FLASH->ACR =
FLASH_ACR_LATENCY_3WS | // Three wait states
FLASH_ACR_PRFTEN * 1 | // Prefetch enable
FLASH_ACR_ICEN * 1 | // Instruction cache enable
FLASH_ACR_DCEN * 1 | // Data cache enable
FLASH_ACR_ICRST * 0 | // Instruction cache reset
FLASH_ACR_DCRST * 0; // Data cache reset

/* Check PLL on, switch to PLL */
while ((RCC->CR & RCC_CR_PLLRDY) != RCC_CR_PLLRDY) { }
RCC->CFGR |= RCC_CFGR_SW_PLL;
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) { }
}