library ieee;
use ieee.std_logic_1164.all;

library altera_mf;
use altera_mf.altera_mf_components.all;

entity KAA_RAM_shreg is
generic
(
width : natural := 24; -- Разрядность регистра
length : natural := 8 -- Длина сдвигового регистра
);
port
(
clk : in std_logic;
data_in : in std_logic_vector (width - 1 downto 0);
data_out : out std_logic_vector (width - 1 downto 0)
);
end entity;


architecture RTL of KAA_RAM_shreg is
type signal_array is array (length downto 0) of std_logic_vector(width - 1 downto 0); -- Сигналы для подключаения блоков памяти
signal signal_ram : signal_array := (others => (others => '0'));
begin

signal_ram(0) <= data_in; -- Записывам данные в младший адрес памяти

--=====================================================================
-- Генерирование блоков памяти для сдвигового регистра
--=====================================================================
SGREG_RAM_GENERATE : for i in 0 to length - 1 generate
altsyncram_component : altsyncram
generic map
(
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone V",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 1,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 1,
width_a => width,
width_byteena_a => 1
)
port map
(
address_a => "0",
clock0 => clk,
data_a => signal_ram(i),
wren_a => '1',
q_a => signal_ram(i + 1)
);
end generate;

data_out <= signal_ram(length); -- Вдаем данные наружу со старшего разряда памяти
end architecture;

logic [cW-1 : 0] ram [2**pDELAY_W];

logic [pDELAY_W-1 : 0] waddr;
logic [pDELAY_W-1 : 0] raddr;
logic       [cW-1 : 0] rdata;

always_ff @(posedge iclk) begin
  if (ival) begin
    raddr       <= raddr + 1'b1;
    waddr       <= raddr + delay;
    //
    ram[waddr]  <= iwdata;
    rdata       <= ram[raddr];
    //
    ordata      <= rdata;
  end
end