module dff(clk, din, dout);
  input clk;
  input [1:0] din;
  output [1:0] dout;
reg dout;
always @ (posedge clk)
  begin
   dout <= din;
end
endmodule

module top;
   reg clk;
   reg [1:0] in_inf;
   wire [1:0] out_inf;
dff D1 (clk, in_inf, out_inf);

initial // Clock generator
  begin
    clk = 0;
    forever #10 clk = !clk;
  end

initial //in_inf[0]    
  begin
    in_inf[0] = 0;
    #28 in_inf[0] = 1;
    #5 in_inf[0] = 0;
  end
initial    //in_inf[1]    
  begin
    in_inf[1] = 0;
    #48 in_inf[1] = 1;
    #5 in_inf[1] = 0;
  end
endmodule