Цитата(haker_fox @ May 23 2018, 04:46)

При сбросе EMC модуля через RGU возникает hardfault. Уже перечитали документацию. Ничего не помогает. Нет ли у кого внятного примера, как использовать RGU?
Так расшифруйте причину HF. Все возможности для этого есть.
С внешней ОЗУ на LPC43xx не работал, но для SPIFI делал так:
Код
CGU.IDIV.C = PCLK_DIVC - 1 << 2 | B11 | CLK_SRC_ID_PLL1 << 24;
CGU.BASE.SPIFI = B11 | CLK_SRC_ID_IDIVC << 24;
PeripheralOn(BRANCH_CLK_M4_SPIFI);
PeripheralOn(BRANCH_CLK_SPIFI, RGU_RST_SPIFI);
Для USB:
Код
PeripheralOn(BRANCH_CLK_M4_USB0);
PeripheralOn(BRANCH_CLK_USB0, RGU_RST_USB0);
И для всех остальных драйверов - аналогично. HF нет.
CODE
enum RGU_RST {
RGU_RST_CORE = 0,
RGU_RST_PERIPH = 1,
RGU_RST_MASTER = 2,
RGU_RST_none = 3,
RGU_RST_WWDT = 4,
RGU_RST_CREG = 5,
RGU_RST_BUS = 8,
RGU_RST_SCU = 9,
RGU_RST_M0SUB = 12,
RGU_RST_M4 = 13,
RGU_RST_LCD = 16,
RGU_RST_USB0 = 17,
RGU_RST_USB1 = 18,
RGU_RST_DMA = 19,
RGU_RST_SDIO = 20,
RGU_RST_EMC = 21,
RGU_RST_ENET = 22,
RGU_RST_FLASHA = 25,
RGU_RST_EEPROM = 27,
RGU_RST_GPIO = 28,
RGU_RST_FLASHB = 29,
RGU_RST_TIMER0 = 32,
RGU_RST_TIMER1 = 33,
RGU_RST_TIMER2 = 34,
RGU_RST_TIMER3 = 35,
RGU_RST_RITIMER = 36,
RGU_RST_SCT = 37,
RGU_RST_MCPWM = 38,
RGU_RST_QEI = 39,
RGU_RST_ADC0 = 40,
RGU_RST_ADC1 = 41,
RGU_RST_DAC = 42,
RGU_RST_UART0 = 44,
RGU_RST_UART1 = 45,
RGU_RST_UART2 = 46,
RGU_RST_UART3 = 47,
RGU_RST_I2C0 = 48,
RGU_RST_I2C1 = 49,
RGU_RST_SSP0 = 50,
RGU_RST_SSP1 = 51,
RGU_RST_I2S = 52,
RGU_RST_SPIFI = 53,
RGU_RST_CAN1 = 54,
RGU_RST_CAN0 = 55,
RGU_RST_M0APP = 56,
RGU_RST_SGPIO = 57,
RGU_RST_SPI = 58,
RGU_RST_ADCHS = 60
};
//---------------------------------------------------------------------------
//CCU1 branch clocks
enum BRANCH_CLK {
BRANCH_CLK_APB3 =0x000, //APB3 bus clock.
BRANCH_CLK_I2C1 =0x001, //clock to the I2C1 register interface and I2C1 peripheral clock.
BRANCH_CLK_DAC =0x002, //clock to the DAC register interface.
BRANCH_CLK_ADC0 =0x003, //clock to the ADC0 register interface and ADC0 peripheral clock.
BRANCH_CLK_ADC1 =0x004, //clock to the ADC1 register interface and ADC1 peripheral clock.
BRANCH_CLK_CAN0 =0x005, //clock to the C_CAN0 register interface and C_CAN0 peripheral clock.
BRANCH_CLK_APB1 =0x020, //APB1 bus clock.
BRANCH_CLK_MCPWM =0x021, //clock to the PWM Motor control block and PWM Motor control peripheral clock.
BRANCH_CLK_I2C0 =0x022, //clock to the I2C0 register interface and I2C0 peripheral clock.
BRANCH_CLK_I2S =0x023, //clock to the I2S0 and I2S1 register interfaces and I2S0 and I2S1 peripheral clock.
BRANCH_CLK_CAN1 =0x024, //clock to the C_CAN1 register interface and C_CAN1 peripheral clock.
BRANCH_CLK_SPIFI =0x040, //clock for the SPIFI SCKI clock input.
BRANCH_CLK_M4 =0x060, //M4 bus clock.
BRANCH_CLK_M4_SPIFI =0x061, //clock to the SPIFI register interface.
BRANCH_CLK_M4_GPIO =0x062, //clock to the GPIO register interface
BRANCH_CLK_M4_LCD =0x063, //clock to the LCD register interface.
BRANCH_CLK_M4_ENET =0x064, //clock to the Ethernet register interface.
BRANCH_CLK_M4_USB0 =0x065, //clock to the USB0 register interface.
BRANCH_CLK_M4_EMC =0x066, //clock to the External memory controller.
BRANCH_CLK_M4_SDIO =0x067, //clock to the SD/MMC register interface.
BRANCH_CLK_M4_DMA =0x068, //clock to the DMA register interface.
BRANCH_CLK_M4_M4CORE =0x069, //clock to the Cortex-M4 core
BRANCH_CLK_M4_SCT =0x06D, //clock to the SCT register interface.
BRANCH_CLK_M4_USB1 =0x06E, //clock to the USB1 register interface.
BRANCH_CLK_M4_EMCDIV =0x06F, //clock to the EMC with clock divider.
BRANCH_CLK_M4_FLASHA =0x070, //clock to the flash bank A
BRANCH_CLK_M4_FLASHB =0x071, //clock to the flash bank B
BRANCH_CLK_M4_M0APP =0x072, //clock to the M0APP coprocessor.
BRANCH_CLK_M4_ADCHS =0x073, //clock to the ADCHS.
BRANCH_CLK_M4_EEPROM =0x074, //clock to the EEPROM
BRANCH_CLK_M4_WWDT =0x080, //clock to the WWDT register interface.
BRANCH_CLK_M4_UART0 =0x081, //clock to the USART0 register interface.
BRANCH_CLK_M4_UART1 =0x082, //clock to the UART1 register interface.
BRANCH_CLK_M4_SSP0 =0x083, //clock to the SSP0 register interface.
BRANCH_CLK_M4_TIMER0 =0x084, //clock to the timer0 register interface and timer0 peripheral clock.
BRANCH_CLK_M4_TIMER1 =0x085, //clock to the timer1 register interface and timer1 peripheral clock.
BRANCH_CLK_M4_SCU =0x086, //clock to the System control unit register interface.
BRANCH_CLK_M4_CREG =0x087, //clock to the CREG register interface.
BRANCH_CLK_M4_RITIMER =0x0A0, //clock to the RI timer register interface and RI timer peripheral clock.
BRANCH_CLK_M4_UART2 =0x0A1, //clock to the UART2 register interface.
BRANCH_CLK_M4_UART3 =0x0A2, //clock to the UART3 register interface.
BRANCH_CLK_M4_TIMER2 =0x0A3, //clock to the timer2 register interface and timer2 peripheral clock.
BRANCH_CLK_M4_TIMER3 =0x0A4, //clock to the timer3 register interface and timer3 peripheral clock.
BRANCH_CLK_M4_SSP1 =0x0A5, //clock to the SSP1 register interface.
BRANCH_CLK_M4_QEI =0x0A6, //clock to the QEI register interface and QEI peripheral clock.
BRANCH_CLK_PERIPH =0x0C0, //clock to the peripheral bus and the Cortex-M0 subsystem AHB multilayer matrix.
BRANCH_CLK_PERIPH_CORE =0x0C2, //clock to the Cortex-M0 subsystem core.
BRANCH_CLK_PERIPH_SGPIO =0x0C3, //clock to the SGPIO interface.
BRANCH_CLK_USB0 =0x0E0, //USB0 peripheral clock.
BRANCH_CLK_USB1 =0x100, //USB1 peripheral clock.
BRANCH_CLK_SPI =0x120, //clock to the SPI interface.
BRANCH_CLK_ADCHS =0x140, //ADCHS clock.
//CCU2 branch clocks
BRANCH_CLK_AUDIO =0x200, //audio system (I2S) clock.
BRANCH_CLK_UART3 =0x220, //USART3 peripheral clock.
BRANCH_CLK_UART2 =0x240, //USART2 peripheral clock.
BRANCH_CLK_UART1 =0x260, //UART1 peripheral clock.
BRANCH_CLK_UART0 =0x280, //USART0 peripheral clock.
BRANCH_CLK_SSP1 =0x2A0, //SSP1 peripheral clock.
BRANCH_CLK_SSP0 =0x2C0, //SSP0 peripheral clock.
BRANCH_CLK_SDIO =0x2E0 //SD/MMC peripheral clock.
};
//return: 1 - если соотв.периферия доступна (включена, затактирована).
int PeripheralReady(BRANCH_CLK branchClk)
{
CCU_CFG_STAT volatile *p = &CCU1.BRANCH[0];
if (branchClk >> 9) p = &CCU2.BRANCH[0];
return p[branchClk & B9 - 1].STAT & B0;
}
void PeripheralResetOn(RGU_RST periph)
{
if (periph == RGU_RST_none) return;
__DMB();
/// *BITBAND_IO(&RGU.CTRL[periph >> 5], periph & B5 - 1) = 1;
///
u64 q = 1ull << periph | 1ull << RGU_RST_M0APP | 1ull << RGU_RST_M0SUB;
if (periph >> 5) q >>= 32;
RGU.CTRL[periph >> 5] = q;
}
void PeripheralResetOff(uint periph)
{
if (periph == RGU_RST_none) return;
*BITBAND_IO(&RGU.CTRL[periph >> 5], periph & B5 - 1) = 0;
__DMB();
}
//Подаёт импульс RESET (или снимает постоянный RESET) на указанную периферию.
//И включает её ветвь тактирования. Не конфигурит базовую частоту!
void PeripheralOn(BRANCH_CLK branchClk, RGU_RST periphRst)
{
CCU_CFG_STAT volatile *p = &CCU1.BRANCH[0];
if (branchClk >> 9) p = &CCU2.BRANCH[0];
p += branchClk & B9 - 1;
p->CFG = B0;
while (!(p->STAT & B0));
if (periphRst == RGU_RST_none) return;
PeripheralResetOn(periphRst); ///
/// int i = 1;
/// if (periphRst == RGU_RST_M0SUB || periphRst == RGU_RST_M0APP) i = 0;
/// *BITBAND_IO(&RGU.CTRL[periphRst >> 5], periphRst & B5 - 1) = i;
while (!*BITBAND_IO(&RGU.ACTIVE[periphRst >> 5], periphRst & B5 - 1));
__DMB();
}
сорри: исходник захламлен, так как проект не был закончен, но периферия работала и так.
Цитата(Arlleex @ May 23 2018, 08:01)

Почему это? Если сработал WDT, о какой прошивке должна идти речь? Как раз-таки после сброса по WDT загрузчик должен быть пропущен и должно запуститься снова приложение, на мой взгляд.
Что мешает делать после приёма прошивки рестарт по WDT?