signal din_sw : std_logic := '0';
signal din, dout_odd, dout_even : std_logic_vector(13 downto 0) := (others => '0');
--

process(CLK)
begin
    if (rising_edge(CLK)) then
        din_sw <= not din_sw;
        if (din_sw = '0') then
            dout_odd <= din;    -- нечетные
        else
            dout_even <= din;    -- четные
        end if;
    end if;
end process;