//////////////////////////////////// ERASE BLOCK  /////////////////////////////
   SPI2_CS0_OFF;
   SPI_rw_flash(NAND_FLASH_BLOCK_ERASE, &dummy);
   temp = 0 | (block_addr >> 10);
   SPI_rw_flash(temp, &dummy);  // Dummy+A16
   temp = block_addr >> 8;
   SPI_rw_flash(temp, &dummy);   //A15-A8
   temp =( block_addr<<3) | page_addr;
   SPI_rw_flash(temp, &dummy);   //A7-A0
   SPI2_CS0_ON;

uint32_t NFLASH_WriteEnable(void)
{
uint8_t dummy, l_error, status;
uint32_t timeout = 0, count_cycles;

do
{
SPI2_CS0_OFF;
l_error = SPI_TransferByte(SPI2_BASE_PTR, NAND_FLASH_WRITE_ENABLE , &dummy);
SPI2_CS0_ON;

for(count_cycles = 0; count_cycles < NAND_FLASH_TIME_OUT; count_cycles++);

SPI2_CS0_OFF;

l_error |= SPI_TransferByte(SPI2_BASE_PTR, NAND_FLASH_GET_FEATURES, &dummy);
l_error |= SPI_TransferByte(SPI2_BASE_PTR, NAND_FLASH_STATUS_REGISTER_ADDRESS, &dummy);
l_error |= SPI_TransferByte(SPI2_BASE_PTR, 0x0, &status);

SPI2_CS0_ON;

for(count_cycles = 0; count_cycles < NAND_FLASH_TIME_OUT; count_cycles++);

if (timeout++ > NAND_FLASH_TIMEOUT)
return NAND_FLASH_WE_FAIL;

}
while ((status & WEL) == 0); //write enable flag

return NAND_FLASH_OK;
}
uint32_t NFLASH_CheckErase(void)
{
uint8_t dummy, l_error, status;
uint32_t timeout = 0, count_cycles;

do
{
SPI2_CS0_OFF;
l_error |= SPI_TransferByte(SPI2_BASE_PTR, NAND_FLASH_GET_FEATURES, &dummy);
l_error |= SPI_TransferByte(SPI2_BASE_PTR, NAND_FLASH_STATUS_REGISTER_ADDRESS, &dummy);
l_error |= SPI_TransferByte(SPI2_BASE_PTR, 0x0, &status);
SPI2_CS0_ON;

if ( timeout++ > NAND_FLASH_TIMEOUT)
return NAND_FLASH_ERASE_FAIL;

for(count_cycles = 0; count_cycles < NAND_FLASH_TIME_OUT; count_cycles++);
}
while ((status & ERS_F) == 1); //erase fail flag

return NAND_FLASH_OK;
}
uint32_t NFLASH_BlockErase(uint32_t block_addr)
{
uint8_t dummy, l_error, temp;
uint32_t count_cycles;
uint32_t status;

//status = NFLASH_CheckBusy();

//if (status == NAND_FLASH_OK)
//{
status = NFLASH_WriteEnable();
if (status == NAND_FLASH_OK)
{
SPI2_CS0_OFF;
l_error = SPI_TransferByte(SPI2_BASE_PTR, NAND_FLASH_BLOCK_ERASE, &dummy);
temp = block_addr >> 16;
l_error |= SPI_TransferByte(SPI2_BASE_PTR, temp, &dummy); // Dummy+A16
temp = block_addr >> 8;
l_error |= SPI_TransferByte(SPI2_BASE_PTR, temp, &dummy); //A15-A8
temp = block_addr & 0xFF;
l_error |= SPI_TransferByte(SPI2_BASE_PTR, temp, &dummy); //A7-A0
SPI2_CS0_ON;

for(count_cycles = 0; count_cycles < NAND_FLASH_TIME_OUT; count_cycles++);

status = NFLASH_CheckErase();
if (status != NAND_FLASH_OK)
return status;
}
else
return status;
//}
//else
//return status;

return NAND_FLASH_OK;
}

row_address = (block_address<<6) | (page_address&0x3F);
NFLASH_BlockErase(row_address );