set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to QSFPA_rx*
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to QSFPA_tx*
set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to QSFPA_rx*
set_instance_assignment -name OUTPUT_TERMINATION "OCT 100 OHMS" -to QSFPA_tx*
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE "1_0V" -to QSFPA_rx*
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE "1_0V" -to QSFPA_tx*
set_instance_assignment -name XCVR_VCCA_VOLTAGE "3_0V" -to QSFPA_rx*
set_instance_assignment -name XCVR_VCCA_VOLTAGE "3_0V" -to QSFPA_tx*
set_instance_assignment -name XCVR_TX_VOD "50" -to QSFPA_tx*

phy_10gbaser_s5gx #(
.CHANNELS (CH_NUM ),
.RESET_MGT_CLK_FREQ (25 ),
.CONFIG_BUS_CLK_FREQ(25 ),
.PHY_REF_CLK_FREQ ("322.265625 MHz")
) i_phy_10gbaser_s5gx_a (
.reset_mgt_clk (clk_25 ),
.reset_mgt_rstn (~rst_25 ),
.phy_ref_clk (clk_phy ),
.phy_mgt_clk (clk_100 ),
.dom_present (1'b1 ),
.dom_rstn ( ),
.ip_rstn ({CH_NUM{1'b1}} ),
.xgmii_clk (a_xgmii_clk ),
.xgmii_clk_rdy (a_xgmii_clk_rdy),
.xgmii_rstn (a_xgmii_rstn ),
.config_bus_clk (clk_25 ),
.config_bus_rstn( ),
.xgmii_tx (a_xgmii_tx ),
.xgmii_rx (a_xgmii_rx ),
.serial_tx (serial_tx),
.serial_rx (serial_rx ),
.phy_debug_out (a_phy_debug_out)
);

phy_10gbaser_s5gx #(
.CHANNELS (CH_NUM ),
.RESET_MGT_CLK_FREQ (25 ),
.CONFIG_BUS_CLK_FREQ(25 ),
.PHY_REF_CLK_FREQ ("322.265625 MHz")
) i_phy_10gbaser_s5gx_b (
.reset_mgt_clk (clk_25 ),
.reset_mgt_rstn (~rst_25 ),
.phy_ref_clk (clk_phy ),
.phy_mgt_clk (clk_100 ),
.dom_present (1'b1 ),
.dom_rstn ( ),
.ip_rstn ({CH_NUM{1'b1}} ),
.xgmii_clk (b_xgmii_clk ),
.xgmii_rstn (b_xgmii_rstn ),
.config_bus_clk (clk_25 ),
.config_bus_rstn( ),
.xgmii_tx (b_xgmii_tx ),
.xgmii_rx (b_xgmii_rx ),
.serial_tx (serial_rx ),
.serial_rx (serial_tx ),
.phy_debug_out (b_phy_debug_out)
);

Info: Can be connected to I port of stratixv_io_obuf WYSIWYG

# parsing Altera .qip|.sip files. Creating list of source files for the IP core.
proc qip_export {fname {out_lib "work"} {out_dir "./out"} } {
# fname - input qip file
# out_lib - name of library if library not defined in the qip
# out_dir - destination folder

puts ">>> qip_export: file:$fname -> lib:$out_lib -> out:$out_dir"

set fname [file normalize $fname]
set qip_dir [file dirname $fname]
puts "Export qip source file:\n qip : $fname\n qip_dir: $qip_dir\n out : $out_dir"

set fi [open $fname "r"]
set lines [split [read $fi] "\n"]
close $fi

set qip_list [list]
set out_list [list]
set ::quartus(qip_path) $qip_dir

foreach line $lines {
puts ">>$line"
if {[regexp -- {^\#} $line]} {
continue
}

if {![regexp -- {^\s*set_global_assignment\s+.*?-name\s+(\w+)\s+((?:\[.+?\])|(?:\".+\")|(?:\$.+))} $line -> kind path_cmd]} {
continue
}
set in_fname [rel_name [subst $path_cmd] $qip_dir]
set ip_name [file rootname [file tail $in_fname]]

set src_fname [lexnormalize [file join $qip_dir $in_fname]]
set out_fname [file join $out_dir $in_fname]

if {![regexp -- {-library\s+((?:\"\w+\")|(?:\w+))} $line -> lib_name]} {
set lib_name $out_lib
}
set lib_name [string map {\" {}} $lib_name]

switch $kind {
"QIP_FILE" {
lappend qip_list $src_fname
}
"VERILOG_FILE" -
"VHDL_FILE" -
"SYSTEMVERILOG_FILE" {
lappend out_list [list $kind $lib_name $src_fname $out_fname]

puts "qip_export:\n $kind\n $lib_name\n $in_fname\n $src_fname\n $out_fname"
}

default {
#puts ">>"
}
}
}
# recursive process included QIP
foreach qip_file $qip_list {
lappend out_list {*}[qip_export $qip_file $out_lib "$out_dir/$ip_name"]
}

return $out_list
}