type packet_t is array (12 downto 0) of std_logic_vector(7 downto 0);
type packet_fifo_t is array (31 downto 0) of packet_t;

signal tx_mailbox_fifo : packet_fifo_t;

shared variable g_fifo_head_idx : integer range 0 to 255 := 0;
shared variable g_fifo_tail_idx : integer range 0 to 255 := 0;

when ST_RAM_TO_TX_BUF_3 =>
    if (idx2 < 13) then
     tx_mailbox_fifo(g_fifo_head_idx)(idx2) <= slave_data_out2;
         idx2 := idx2 + 1;
    else
    --get ready the next fifo slot
    g_fifo_head_idx := g_fifo_head_idx + 1;
    if (g_fifo_head_idx > 31) then
        g_fifo_head_idx := 0;
     end if;
        RamState_b <= ST_RAMB_IDLE;    
   end if;

TX_MAILBOX_FIFO_MANAGER: process (REG_CLK)
begin
    if (rising_edge(REG_CLK)) then
    
    --send previous message - g_fifo_head_idx incremeted by 1 in other process
        if (g_fifo_tail_idx < g_fifo_head_idx)    then      
        tx_buf_ready <= '1';        
        end if;
            
    if (update_tail_idx = '1') then
        tx_buf_ready <= '0';
        g_fifo_tail_idx := g_fifo_tail_idx + 1;
        if (g_fifo_tail_idx > 31) then
        g_fifo_tail_idx := 0;
        end if;
    end if;
    
    end if;
end process TX_MAILBOX_FIFO_MANAGER;

when ST_TX_DATA =>  --send 13 byte of data
    if (tx_byte_idx < 13) then
        MSPI_WR_DATA <= X"00" & tx_mailbox_fifo(g_fifo_tail_idx)(tx_byte_idx);
              
    MSPI_WR_START_TRIG <= '1'; --send a byte
                          
    tx_byte_idx := tx_byte_idx + 1;    
                          
    NextState <= ST_TX_DATA;
    McpState <= ST_WAIT_DONE;
    else
    MSPI_CS <= '1';            --chip select high
      
        update_tail_idx <= '1';

    NextState <= ST_MCP_IDLE;
    McpState <= ST_REQ_TO_SEND0;
    end if;

component fifo IS     port
     (
         clock            : in std_logic;
         data            : in std_logic_vector (7 DOWNTO 0);
         rdreq            : in std_logic;
         sclr            : in std_logic;
         wrreq            : in std_logic;
         almost_empty : out std_logic;
         almost_full     : out std_logic;
         empty            : out std_logic;
         full            : out std_logic;
         q               : out std_logic_vector (7 DOWNTO 0);
         usedw            : out std_logic_vector (8 DOWNTO 0)
     );
end component;

U_FIFO : fifo    
   port map
   (
      clock            => REG_CLK,
       data            => fifo_data_in,
       rdreq            => fifo_rdreq,    
       sclr            => '0',
       wrreq            => fifo_wrreq,
       almost_empty  => fifo_almost_empty,
       almost_full     => fifo_almost_full,
       empty            => fifo_empty,
       full            => fifo_full,
       q               => fifo_data_out,
       usedw            => fifo_usedw
   );

FIFO_INTERFACE : process (REG_CLK) variable fifo_idx : integer range 0 to 255 := 0;
begin
     if (rising_edge(REG_CLK)) then
          
           case FifoState is
          
               when ST_FIFO_IDLE =>
                
                     fifo_idx := 0;
                      
                      debug_val4 <= fifo_usedw(7 downto 0);
                      
                     if (fifo_write = '1') then
                          if (fifo_almost_full = '0') then
                              FifoState <= ST_FIFO_WRITE;
                         end if;                
                      end if;
            
             when ST_FIFO_WRITE =>     --continious write to FIFO
                     if (cs2 = '0') then   --chip select low
                          if (rx_rdy4 = '1') then  --byte received
                               fifo_wrreq <= '1';
                                 fifo_data_in <= sspi_data_in;
                                 fifo_idx := fifo_idx + 1;
                                 debug_val1 <= debug_val1 + '1';
                             end if;
                            
                           if (fifo_idx > 13) then  --overflow protection
                                fifo_idx := 0;
                               fifo_wrreq <= '0';
                              FifoState <= ST_FIFO_IDLE;
                           end if;        
                      else
                          fifo_idx := 0;
                           fifo_wrreq <= '0';
                          FifoState <= ST_FIFO_IDLE;              
                      end if;            
           end case;  
    
     end if;    
              
end process FIFO_INTERFACE;