always @ (state) begin
    case (state)
        S0:    data_out = data_in;
        s1:    data_out = data_in;
        ...
        S71:    data_out = data_in;
    
    endcase
end

always @ (posedge clk or negedge reset)
begin
    if (!reset)
            state <= S0;
        else
            case (state)
                S0:    begin
                        if (ss)
                            state <= S1;
                        else
                            state <= S0;
                        end
                S1:    begin
                        if (ss)
                            state <= S2;
                        else
                            state <= S1;
                        end
                                      ...

                S70:    begin
                        if (ss)
                            state <= S71;
                        else
                            state <= S70;
                        end
                S71:
                            state <= S71;
            endcase
    end

assign data_out = data_in;

always @ (posedge clk or negedge reset)
begin
    if (!reset)
        state <= S0;
    else
        if (ss & (state != S71))
             state <= state + 1'b1;
end