......
signal EO : std_logic;
signal Write_Hi : std_logic;
......
output: process (clk) --такт с периодом 10 ns
begin
if (clk'event and clk='1')
then
  
  if (EO='1') then
     if (Write_Hi='1')
     then
       DO<=DI(15 downto 8);
     else
       DO<=DI(7 downto 0);
     end if;
  else
   ........
  end if;
end if;
end process output;

.....
.....

entiny XXX is
   port (
      clk : in std_logic; -- тактовый сигнал с периодом в 10 нс
      rst : in std_logic; -- сброс
      ena : in std_logic; -- сигнал разрешения
      byte1 : in std_logic_vector (7 downto 0);
      byte2 : in std_logic_vector (7 downto 0);
      byte_out : out std_logic_vector (7 downto 0)
   );
end XXX;

architecture behav of XXX is  

type tstate is (sm_Idle, sm_Byte2);

signal state : tstate;

sm_proc: process (clk, rst)
begin
  if rst = '1' then
    state <= sm_Idle;
  elsif rising_edge(clk) then
    case state of
      when sm_Idle =>
          if ena = '1'  then
             state <= sm_Byte2;
             byte_out <= byte1;
          end if;
      when sm_Byte1 =>
          byte_out <= byte2;
          state <= sm_Idle;
     end case;
  end if;
end process;

end XXX;