Полная версия этой страницы: Virtex-5, господа
Форум разработчиков электроники ELECTRONIX.ru > Программируемая логика ПЛИС (FPGA,CPLD, PLD) > Работаем с ПЛИС, области применения, выбор
Цитата(maior @ May 15 2006, 15:08) 
класно, дайте 2
интересно когда появяться.
Стоит подписаться на evaluation board: если будет promotion - может быть очень дешево:
http://www.xilinx.com/xlnx/xebiz/productvi...Virtex-5+Boards
http://www.xilinx.com/xlnx/xebiz/productvi...Virtex-5+Boards
Интересно, какие будут цены?
Цитата(maior @ May 16 2006, 07:24)
Стоит подписаться на evaluation board: если будет promotion - может быть очень дешево:
http://www.xilinx.com/xlnx/xebiz/productvi...Virtex-5+Boards
http://www.xilinx.com/xlnx/xebiz/productvi...Virtex-5+Boards
хмм на фото калеки изображены, даже обычного писая нет
Похоже, что и Альтера переходит на семейство 65нм fpga:
Altera is targeting the second half of 2006 for the launch of its first 65nm product, the Stratix III family.
The firm claimed the migration to 65nm will double the density over 90nm and deliver an average performance improvement of about 20 per cent, compared to 90nm, and a power consumption improvement of 50 per cent at the same frequency.
“If we hadn’t changed anything then going from 90nm to 65nm, without any innovation, would double the density and double the power consumption,” said Tim Colleran, vice-president for European business operations at Altera.
“We wanted to make the chip faster. It’s not a leakage problem, it’s all those transistors toggling all together on a very large chip,” added Colleran. Top of the range transistor count will be around one billion.
The innovation which increased the speed of Stratix III, lowered power consumption and doubled density is having user-programmable blocks set for varying levels of power consumption and frequency.
They can only be programmed once. “It’s performance when you need it, low power everywhere else,” said Colleran. “We find that 80 per cent of a chip is low power.”
Altera is doing eight test chips for various different functions of Stratix III. “All the different functions are being tested on individual chips before integrating them on one chip,” said Colleran. Final validation is scheduled for May.
Altera is using its redundancy technology in Stratix III which can add up to 10 per cent on the die size but delivers, said Altera, what amounts to a seven to eight times improvement in the early yields.
Stratix III will be made by TSMC. “There will be materials changes at 65nm over 90nm,” said Colleran, but he wouldn’t say what they would be. However, strained silicon and SoI are two technologies Altera is looking at, according to Colleran.
Источник: http://www.electronicsweekly.com/Articles/...nsecondhalf.htm
Altera is targeting the second half of 2006 for the launch of its first 65nm product, the Stratix III family.
The firm claimed the migration to 65nm will double the density over 90nm and deliver an average performance improvement of about 20 per cent, compared to 90nm, and a power consumption improvement of 50 per cent at the same frequency.
“If we hadn’t changed anything then going from 90nm to 65nm, without any innovation, would double the density and double the power consumption,” said Tim Colleran, vice-president for European business operations at Altera.
“We wanted to make the chip faster. It’s not a leakage problem, it’s all those transistors toggling all together on a very large chip,” added Colleran. Top of the range transistor count will be around one billion.
The innovation which increased the speed of Stratix III, lowered power consumption and doubled density is having user-programmable blocks set for varying levels of power consumption and frequency.
They can only be programmed once. “It’s performance when you need it, low power everywhere else,” said Colleran. “We find that 80 per cent of a chip is low power.”
Altera is doing eight test chips for various different functions of Stratix III. “All the different functions are being tested on individual chips before integrating them on one chip,” said Colleran. Final validation is scheduled for May.
Altera is using its redundancy technology in Stratix III which can add up to 10 per cent on the die size but delivers, said Altera, what amounts to a seven to eight times improvement in the early yields.
Stratix III will be made by TSMC. “There will be materials changes at 65nm over 90nm,” said Colleran, but he wouldn’t say what they would be. However, strained silicon and SoI are two technologies Altera is looking at, according to Colleran.
Источник: http://www.electronicsweekly.com/Articles/...nsecondhalf.htm
Ну и чем этот виртекс 5 лучше того же стратикса2, кроме 65нм технологии, на первый взгляд ресурсы и причендалы теже?
Кстати кроме стратикс3 вроде как и циклон3 обещают тоже 65нм.
Кстати кроме стратикс3 вроде как и циклон3 обещают тоже 65нм.
Цитата(Magnum @ May 17 2006, 20:56)
Ну и чем этот виртекс 5 лучше того же стратикса2, кроме 65нм технологии, на первый взгляд ресурсы и причендалы теже?
Кстати кроме стратикс3 вроде как и циклон3 обещают тоже 65нм.
Кстати кроме стратикс3 вроде как и циклон3 обещают тоже 65нм.
холивар думаю устраивать смысла нет,
каждый сделает собственные выводы, поэтому ИМХО лучше что бы каждый сравнил сам структуру ALM и SLICEM(SLICEL).
Цитата(Magnum @ May 18 2006, 05:56)
Ну и чем этот виртекс 5 лучше того же стратикса2, кроме 65нм технологии, на первый взгляд ресурсы и причендалы теже?
LUT либо шесть входов/один выход либо пять входов/два выхода плюс некоторые вкусности в синтезе и разводке частот. Потом, выводы питания расположены так, что все питание теоретически можно развести в одном слое.
Цитата(Gate @ May 17 2006, 20:30)
<cut>...They can only be programmed once... <cut>
С этого места по подробней пожайлуста...
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