A continuing debate will consider whether the ALM or Xilinx's 6-input lookup-table approach in its just-released Virtex 5 line (see page 1, May 15) is the more-efficient approach for the basic logic building block, said Paul Ekas, senior product marketing manager for high-density FPGA products at Altera. The ALM's flexibility allows designers to pack multiple lookup tables (LUTs) into a single ALM, Ekas said, citing density experiments that showed two tables can be configured into a single ALM about 80 percent of the time.

"Furthermore, about 40 percent of the time two 4-input LUTs can fit in an ALM, and about 24 percent of the time two 5-input LUTs can fit in a single ALM." Ekas calls Xilinx's 6-input LUT less-flexible. "Although it has the ability to pack two 5-input LUTs in one 6-input element, he said, "the LUT must share many inputs and thus the packing will rarely happen." Ekas also estimates that 63 percent of the time, the 6-input LUT will not be fully used.

A continuing debate will consider whether the ALM or Xilinx's 6-input lookup-table approach in its just-released Virtex 5 line (see page 1, May 15) is the more-efficient approach for the basic logic building block, said Paul Ekas, senior product marketing manager for high-density FPGA products at Altera. The ALM's flexibility allows designers to pack multiple lookup tables (LUTs) into a single ALM, Ekas said, citing density experiments that showed two tables can be configured into a single ALM about 80 percent of the time.

"Furthermore, about 40 percent of the time two 4-input LUTs can fit in an ALM, and about 24 percent of the time two 5-input LUTs can fit in a single ALM." Ekas calls Xilinx's 6-input LUT less-flexible. "Although it has the ability to pack two 5-input LUTs in one 6-input element, he said, "the LUT must share many inputs and thus the packing will rarely happen." Ekas also estimates that 63 percent of the time, the 6-input LUT will not be fully used.