#pragma NOINIT                                                            
const unsigned long code_protection __at 0x1FC = 0x87654321;

20.7 Code Read Protection (CRP)
Code read protection is enabled by programming the flash address location 0x1FC (User
flash sector 0) with value 0x8765 4321 (2271560481 Decimal). Address 0x1FC is used to
allow some room for the fiq exception handler. When the code read protection is enabled
the JTAG debug port, external memory boot and the following ISP commands are
disabled:
• Read Memory
• Write to RAM
• Go
• Copy RAM to Flash
The ISP commands mentioned above terminate with return code
CODE_READ_PROTECTION_ENABLED. The ISP erase command only allows erasure
of all user sectors when the code read protection is enabled. This limitation does not exist
if the code read protection is not enabled. IAP commands are not affected by the code
read protection.
Important: CRP is active/inactive once the device has gone through a power cycle.

                ORG    0x1FC
                dc32    0         // Protect Label place - protect if 0x87654321

0x7FFFD000 E59FF018  LDR    PC, [PC, #+24]      ; [0x7FFFD020] =0x7FFFD1BC
.................
0x7FFFD1BC E59F0018  LDR    R0, [PC, #+24]      ; [0x7FFFD1DC] =SCCSPR (0xE01FC184)
0x7FFFD1C0 E51F1014  LDR    R1, [PC, #-20]       ; [0x7FFFD1B4] =0x1FC
0x7FFFD1C4 E5912000  LDR    R2, [R1, #+0]
0x7FFFD1C8 E5802000  STR    R2, [R0, #+0]
0x7FFFD1CC E51F2188  LDR    R2, [PC, #-392]     ; [0x7FFFD04C] =RAMEND (0x40007FFF)
0x7FFFD1D0 E242D01F  SUB    SP, R2, #0x1F
0x7FFFD1D4 E59FE004  LDR    LR, [PC, #+4]        ; [0x7FFFD1E0] =0x7FFFD3AB
0x7FFFD1D8 E12FFF1E  BX     LR

RSIR Function Description Reset
Value
0 POR
Assertion of the POR signal sets this bit, and clears all of the other bits in this register. But
if another Reset signal (e.g., External Reset) remains asserted after the POR signal is
negated, then its bit is set. This bit is not affected by any of the other sources of Reset.
see text
1 EXTR Assertion of the RESET signal sets this bit. Ths bit is cleared by POR, but is not affected by
WDT or BOD reset.
2 WDTR This bit is set when the Watchdog Timer times out and the WDTRESET bit in the Watchdog
Mode Register () is 1. It is cleared by any of the other sources of Reset.
3 BODR
This bit is set when the 3.3V power falls below 2.6V. If the voltage continues to decline o the
level at which POR is asserted (nominally 1V), this bit is cleared, but if the voltage comes
back up without reaching that level, this bit remains 1. This bit is not affected by External
Reset nor Watchdog Reset.
7:4 Reserved Reserved, user software should not write ones to reserved bits. 0

intvect:00000000                 LDR     R2, =0xE002C014
intvect:00000004                 MOV     R3, #0
intvect:00000008                 SWP     R0, R3, [R2]

  00000000  E59F4034  LDR          R4, [PC, #+52]
  00000004  E3A05002  MOV          R5, #0x2          
  00000008  E5845000  STR          R5, [R4, #+0]    
  0000000C  E3A05003  MOV          R5, #0x3          
  00000010  E5845004  STR          R5, [R4, #+4]    
  00000014  E59F201C  LDR          R2, [PC, #+28]          ; [0x38] =0xE002C014
  00000018  E3A03000  MOV          R3, #0x0          
  0000001C  E1020093  SWP          R0, R3, [R2]      
  00000020  E2822028  ADD          R2, R2, #0x28
  00000024  E1021093  SWP          R1, R3, [R2]